Help me make a glitch free reset logic

[sudhirkv]

Hi

I have to design a glitch free reset logic where my design runs with 50MHz. There is a reset switch and the FPGA what am using will get the input from the switch and i have to give the reset to other peripherals. Lets say the output to other peripherls is resetout.

Initially i just assigned the resetout to to input reset

assign resetout = reset;

I had lot to glitches due to the switch debouce.

So i sampled the reset as

always @ (posedge clk) // 50Mhz Clk
reset1 <= reset;
resetout <= reset1;

now the glitches reduced but not satisfactory.

Is there any other way to remove the glitches completely.

 

[mukesh1981]

Glitch Free Reset

Hi
In this case only less than one clock cycle glitch u can remove. If u want capture reset signal which is high more than one clock cycle ,for that u have to use frequency divider . Use this frequency for the synchronization u can further remove glitch on the reset signal.

 

[echo47]

Glitch Free Reset

Try sampling the reset signal at 50 Hz or less instead of 50 MHz. That's how I do all my button/switch debouncing.

 

[manasiw2]

Re: Glitch Free Reset

Hi,
Pass your reset through a shift register, number of shifts can be decided by how much time you want to check the reset input,check output of shift register stages and use that as your final signal for reset.