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#### Aigneryu

##### Member level 3
but when I type "ncverilog top.v cell.v" as what I did in verilog-XL
the simulator will not launch unless I type "ncverilog top.v cell.v +access+r"

Moreover, if I have to attach a cell based lib cell_lib.v to run simulation,
I write "uselib file= /path/cell_lib.v" in my netlist, and the verilog-XL runs well, while ncverilog will not run with certain warning messages. In fact, I found that as soon as I put the uselib syntax in my netlist, the ncverilog will not launch.

How can it be like this? Can somebody help me? or show me some examples to use nc-verilog in command line mode.

#### aramis

##### Member level 3
ncvlog uselib error

Aigneryu said:
but when I type "ncverilog top.v cell.v" as what I did in verilog-XL
the simulator will not launch unless I type "ncverilog top.v cell.v +access+r"

Moreover, if I have to attach a cell based lib cell_lib.v to run simulation,
I write "uselib file= /path/cell_lib.v" in my netlist, and the verilog-XL runs well, while ncverilog will not run with certain warning messages. In fact, I found that as soon as I put the uselib syntax in my netlist, the ncverilog will not launch.

How can it be like this? Can somebody help me? or show me some examples to use nc-verilog in command line mode.

It's strange, may i ask you a question??
which version of ncverilog do you use??

and i think `uselib is the syntax of verilog-XL instead of verilog
so check out your document of ncverilog to find out this.

besides, instead of using 'uselib syntax i always use "-y path of lib" as input of ncverilog command, it works well in pre-sim!!

good luck

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