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help me in reducing the spikes in inverter

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prasadel06

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hi....

i am using inverter in my project....i am using 130 nm tech...
and i am getting spikes...please help me in reducing the spikes in
the output of the inverter...

thank you..
prasad
 

carv_13

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can you post a snap of the spikes that you are getting?. Did you try increasing the width of the PMOS?.
 

barrybear

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Where ever you get a very high speed swithing junction you will get a spike. try a little decoupling. Shunting with a small capacitor.Diodes can also help as clamps,
 

funnynypd

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Diode and cap will definitely help. The cap might slow down the max speed.
 

prasadel06

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hi....
here i am using 130 nm tech and with cap 2.5f
here i am attaching snapshot of output..
thanks
[/img]
 

phutanesv

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prasadel06 said:
hi....
here i am using 130 nm tech and with cap 2.5f
thanks

Then u need to adjust with the width, make sure that pmos is 2or 3 times more the width of nmos .

Also just see if ur are geting the rise time and fall time properly for that

capacitor value.


Regards
Phutane
 

onlymusic16

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Yes i also agree to what other members are saying. It seems the sizing is the culprit here. Adjust the width of the mosfets (it would be wrong to quote any number here) but let me take a guess, your wp & wn must be large. Is your wp >1. if yes, get it down because it has to drive only a small cap of 2.5f.
 

ericyuan

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Wp/Wn=2.7
try to control the trip-point at the middle of the full voltage
 

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