HELP ME FOR verilog code for USB 3.0 AND STATIC TIME ANALYSI

[naresh naik]

HI FRIENDS,


I AM DOING MY MTECH PROJECT ON USB 3.0 ..... AND I AM NEW TO STATIC TIME ANALYSIS USING SYNOPSYS PRIME TIME.....

PLZ SEND TUTORIAL ON USB AND STATIC TIME ANALYSIS USING SYNOPSYS PRIME TIME .......PLZ SEND VERILOG CODE FOR USB 3.0 TO MY MAILID :

ch_nrshnk@yahoo.co.in .....PLZ HELP ME AS SOON AS POSSIBLE ....

 

[vlsichipdesigner]

Re: HELP ME FOR verilog code for USB 3.0 AND STATIC TIME ANA

hi,

everything you had asked to send to your mail id, what is that you want to do in your project if so, you had asked for tutorial, verilog code and things liket hat.

my friend, please search the web, which has tons of information. ask pointed questions, no spoon feeding help mydear(sorry for advicing). please ask pointed queries.

by the way, you can find information regarding timing analysis, how to write constraints file for STA, how and why to model timing exceptions like false path/multicycle paths, how to solve timing violations if you have in your design, where to look to solve the violations can be located @

https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/asic-knowledge-house.html

myprayers,
chip design made easy
https://www.vlsichipdesign.com