Help me fixing ncvlog compile error

[elone]

A ncvlog compile error ?

This is verilog src:
`celldefine
module add1d1 (A, B, CI, SM, CO);
input A, B, CI;
output SM, CO;

wire int_res_0, int_res_1, int_res_2;

/////////////////////////////////////
// FUNCTIONALITY //
/////////////////////////////////////

xor (SM, A, B, CI);
and (int_res_0, A, B);
and (int_res_1, A, CI);
and (int_res_2, B, CI);
or (CO, int_res_0, int_res_1, int_res_2);

/////////////////////////////////////
// TIMING //
/////////////////////////////////////

specify
specparam tpd_CI_SM_posedge = (0, 0, 0, 0, 0, 0);
specparam tpd_A_SM_posedge = (0, 0, 0, 0, 0, 0);
specparam tpd_B_SM_posedge = (0, 0, 0, 0, 0, 0);
specparam tpd_CI_SM_negedge = (0, 0, 0, 0, 0, 0);
specparam tpd_A_SM_negedge = (0, 0, 0, 0, 0, 0);
specparam tpd_B_SM_negedge = (0, 0, 0, 0, 0, 0);
specparam tpd_CI_CO = (0, 0, 0, 0, 0, 0);
specparam tpd_A_CO = (0, 0, 0, 0, 0, 0);
specparam tpd_B_CO = (0, 0, 0, 0, 0, 0);

(posedge CI => (SM:A)) = tpd_CI_SM_posedge;
(posedge A => (SM:B)) = tpd_A_SM_posedge;
(posedge B => (SM:A)) = tpd_B_SM_posedge;
(negedge CI => (SM:A)) = tpd_CI_SM_negedge;
(negedge A => (SM:B)) = tpd_A_SM_negedge;
(negedge B => (SM:A)) = tpd_B_SM_negedge;
(CI => CO) = tpd_CI_CO;
(A => CO) = tpd_A_CO;
(B => CO) = tpd_B_CO;
endspecify
endmodule
`endcelldefine





This is error :
ncvlog: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
specparam tpd_CI_SM_posedge = (0, 0, 0, 0, 0, 0);
|
ncvlog: *E,NOPPLS (C:/verilog/cl41.v,32|34): illegal syntax except when defining PATHPULSE$ specparam [13.7(IEEE)].

 

[visualart]

parameter number maybe error.
Format is (0:0:0, ..., ...)?

 

[elone]

When i use modelsim compile it, everything is OK ?

 

[joe2moon]

Ambiguity

I have tried to compile above module by different Verilog simulators.
- 1) Verilog-XL:
> verilog add1d1.v
It's o.k.

- 2) NC-Verilog:
> ncxlmode add1d1.v
Error message !

- 3) VCS
> vcs -c add1d1.v
Error message !
---------------------------------------------------------------------------------
But, if modify the timing triplet in add1d1.v to 0.0:0.0:0.0,
then all three simulaors can compile it successfully.
---------------------------------------------------------------------------------

I think maybe it comes from the definition about how to
specify the timing triplet has some ambiguity :?
---------------------------------------------------------------------------------

ps:
I have seen another tool that does not support the triplet format
in original add1d1 module before....

 

[elone]

This is a T$MC stdlib file ! How this happen ?