Help me fix XST errors during synthesis

[nagu guptha]

I have written verilog code for raotaion cordic( to ratate given vector by given input angle) .syntax and simulation works fine, but encountered huge no of errors with synthesis. Please help me to make out the meaning of error below

ERROR:Xst:1706 - Unit <rotation_cordic>: port <l9_44_index0000> of logic node <l9_44_cmp_eq0000> has no source

ERROR:Xst:1706 - Unit <rotation_cordic>: port <mux0005_index0000> of logic node <mux0005_cmp_eq0000> has no source

 

[tariq786]

error:xst:1706

I think if you click in xilinx ise on the error, it can take you to xilinx website, where you can see the solution. Else google using these key words

ERROR:Xst:1706 or

see this page (inside you can find error 1706 solution)

**broken link removed**

 

[nagu guptha]

port of logic node has no source

thank u very much.......,u r guidance is really useful.

 

[king_yiping]

Re: error in synthesis

I have the same problem, and I followed the above instruction, it doesn't work, I don't know why

---------- Post added at 04:45 ---------- Previous post was at 04:40 ----------

A: the behavioral simulation result is right !



B:when comes to synthesize process

ISE 11 gives error information:



ERROR:Xst:1706 - Unit <synapse>: port <i<31>> of logic node <_old_i_7<31>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<30>> of logic node <_old_i_7<30>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<29>> of logic node <_old_i_7<29>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<28>> of logic node <_old_i_7<28>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<27>> of logic node <_old_i_7<27>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<26>> of logic node <_old_i_7<26>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<25>> of logic node <_old_i_7<25>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<24>> of logic node <_old_i_7<24>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<23>> of logic node <_old_i_7<23>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<22>> of logic node <_old_i_7<22>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<21>> of logic node <_old_i_7<21>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<20>> of logic node <_old_i_7<20>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<19>> of logic node <_old_i_7<19>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<18>> of logic node <_old_i_7<18>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<17>> of logic node <_old_i_7<17>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<16>> of logic node <_old_i_7<16>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<15>> of logic node <_old_i_7<15>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<14>> of logic node <_old_i_7<14>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<13>> of logic node <_old_i_7<13>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<12>> of logic node <_old_i_7<12>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<11>> of logic node <_old_i_7<11>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<10>> of logic node <_old_i_7<10>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<9>> of logic node <_old_i_7<9>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<8>> of logic node <_old_i_7<8>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<7>> of logic node <_old_i_7<7>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<6>> of logic node <_old_i_7<6>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<5>> of logic node <_old_i_7<5>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<4>> of logic node <_old_i_7<4>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<3>> of logic node <_old_i_7<3>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<2>> of logic node <_old_i_7<2>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<1>> of logic node <_old_i_7<1>> has no source
ERROR:Xst:1706 - Unit <synapse>: port <i<0>> of logic node <_old_i_7<0>> has no source
ERROR:Xst:1847 - Design checking failed

---------- Post added at 04:50 ---------- Previous post was at 04:45 ----------

C Source Code:


module synapse(sys_clk,neuron_clk,reset,synapse_add,pre_s​pikes,calculate_ready,synapse_output);
parameter prenn=3;
parameter neuron_number=4;

input sys_clk,neuron_clk,reset;
input[15:0] synapse_add;
input[prenn-1:0] pre_spikes;

output calculate_ready;
output[15:0] synapse_output;

reg reg_neuron_clk,neuron_clk_rise;
reg start_calculate,calculate_ready;
reg[15:0] synapse_outputs[neuron_number-1:0];

wire[7:0] rand;

integer i,j;

---------- Post added at 04:54 ---------- Previous post was at 04:50 ----------

always(posedge sys_clk) //plz add char "at" here
begin
if(reset)
begin
calculate_ready<=0;
start_calculate<=0;
i=0;
j=0;
end
else
begin

reg_neuron_clk<=neuron_clk;
neuron_clk_rise<=neuron_clk&(~reg_neuron_clk);

if(neuron_clk_rise)
begin
calculate_ready<=0;
start_calculate<=1;

for(i=0;i<neuron_number;i=i+1)
begin
synapse_outputs<=0;
end

i=0;
end

if(start_calculate)
begin
if(i<prenn&&pre_spikes)
begin
for(j=0;j<neuron_number;j=j+1)
begin
synapse_outputs[j]<=synapse_outputs[j]+rand;
end
i=i+1;
end
else
begin
i=i+1;
end

if(i==prenn)
begin
i=0;
j=0;
start_calculate<=0;
calculate_ready<=1;
end
else
begin
calculate_ready<=0;
end

end
end
end



random_number inst_rand_number(.sys_clk(sys_clk),.reset(reset),.​rand(rand));

assign synapse_output=(calculate_ready==1)?synapse_output​s[synapse_add]:0;


endmodule
D: I followed the instructions given below, but it doesn't work




ERROR:Xst:1706 - Unit <MIPS>: port <step_pulse> of logic node <_n0000> has no source
ERROR:Xst:1847 - Design checking failed

To get around this error, you will have to change the XST FSM (Finite State Machine) options. Do this, right-click on “Synthesis-XST” in the center left panel in Project Navigator. Select “Properties”. Once in the “Process Properties” menu, select the “HDL Options” tab. Then, click on the drop-menu of “FSM Encoding Algorithm”. Change the value from “Auto” to “None”. For some reason, XST is too smart in “Auto” mode and optimizes out the logic that drives the step_pulse signal.






E:




if(i==prenn)
begin
i=0;
j=0;
start_calculate<=0;
calculate_ready<=1; // when changed into calculate_ready<=0, It works OK, very STRANGE!!!
end
else
begin
calculate_ready<=0;
end


..

---------- Post added at 04:55 ---------- Previous post was at 04:54 ----------

Any suggestions or help will be appreciated!!

 

[permute]

Re: error in synthesis

note: post #3 29-04-09 22:27 Another old tread. is the "new thread" function disabled now? It seems like suddenly every post is an addition to an old thread.

in sim, you can see if something is connected using "drivers". eg "drivers /path/to/signal/i". You should track the errors back to warnings which eventually show what the real problem is.

you can also double check the file paths. you might have included the wrong file in the design.