Help me fix this error pls.

[kokei74]

portmap technique

i tried to perform a multiplication using port map technique. For some reason its getting an error. Can some1 help me fix this and tell me the reason?

library ieee;
use ieee.std_logic_1164.all;

entity Phase1 is

port ( clk :IN std_logic;
Mulresult :OUT std_logic_vector (15 downto 0));

end Phase1;

architecture logic of Phase1 is

signal s0 : std_logic;
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;

component CounterA
port (clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;


component CounterB
port (clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;


component ROMA
port (ADDR : in std_logic_vector (3 downto 0); -- address input
DOUT : out std_logic_vector (7 downto 0)); -- data output
end component;


component ROMB
port ( ADDRB : in std_logic_vector (3 downto 0); -- address input
DOUTB : out std_logic_vector (7 downto 0)); -- data output
end component;


component mul
port (a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);

begin

stage0 : CounterA port map (q =>s0,clock=>clk);
stage1 : CounterB port map (q =>s1,clock=>clk);
stage2 : ROMA port map (ADDR =>s0,DOUT=>s2);
stage3 : ROMB port map (ADDRB =>s1,DOUTB=>s3);
stage4 : mul port map (a =>s2,b =>s3,result=>Mulresult);

end logic;

 

[josephlejo]

port map technique

Helloo....

Could you also post what type of error message you are getting..

Also is this the code u typed / copy pasted....

In (component mul ) there is a closing bracket missing in the end of the code.......

 

[kokei74]

i have modify this code from my previous project. For the component i just copy from module that i alrdy done.

lol thx for that 1.. i have change for component mul but still got error..

its said that : Error: Node instance "stage4" instantiates undefined entity "mul"

component mul
port ( a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
end component;

Added after 36 minutes:

problem solve.. thx for ur concern joseph.
but can i still need help to finish up another phase of this project.
Hope u can help me out then.