Help me fix the errors in this VHDL code

[phobos1]

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Value 0 is out of range 3 to 0 (null range).




library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
port(mul1,mul2:in std_logic_vector(3 downto 0);
produt std_logic_vector(7 downto 0));
end multiplier;

architecture arch_multiplier of multiplier is

component adder is
port(a_4,b_4: in std_logic_vector(7 downto 0);
s_4: out std_logic_vector(7 downto 0));
end component;

type arraytype is array(3 to 0) of std_logic_vector(7 downto 0);
--type arraytype1 is array(3 to 0) of std_logic_vector(8 downto 0);
signal temp:arraytype;
signal temp_prod:arraytype;

begin

process(mul1,mul2)

variable temp_mul1:std_logic_vector(15 downto 0):="0000000000000000";


begin

temp_mul1(0):=(mul1(0) and mul2(0));
temp_mul1(1):=(mul1(1) and mul2(0));
temp_mul1(2):=(mul1(2) and mul2(0));
temp_mul1(3):=(mul1(3) and mul2(0));
temp_mul1(4):=(mul1(0) and mul2(1));
temp_mul1(5):=(mul1(1) and mul2(1));
temp_mul1(6):=(mul1(2) and mul2(1));
temp_mul1(7):=(mul1(3) and mul2(1));
temp_mul1(8):=(mul1(0) and mul2(2));
temp_mul1(9):=(mul1(1) and mul2(2));
temp_mul1(10):=(mul1(2) and mul2(2));
temp_mul1(11):=(mul1(3) and mul2(2));
temp_mul1(12):=(mul1(0) and mul2(3));
temp_mul1(13):=(mul1(1) and mul2(3));
temp_mul1(14):=(mul1(2) and mul2(3));
temp_mul1(15):=(mul1(3) and mul2(3));

temp(0)<="0000"&temp_mul1(3)&temp_mul1(2)&temp_mul1(1)&temp_mul1(0);
temp(1)<="000"&temp_mul1(7)&temp_mul1(6)&temp_mul1(5)&temp_mul1(4)&'0';
temp(2)<="00"&temp_mul1(11)&temp_mul1(10)&temp_mul1(9)&temp_mul1(8)&"00";
temp(3)<='0'&temp_mul1(15)&temp_mul1(14)&temp_mul1(13)&temp_mul1(12)&"000";


ad1:adder port map(a_4=>temp(0),b_4=>temp(1),s_4=>temp_prod(0));
ad2:adder port map(a_4=>temp_prod(0),b_4=>temp(2),s_4=>temp_prod(1));
ad3:adder port map(a_4=>temp_prod(1),b_4=>temp(3),s_4=>temp_prod(2));

prod<=temp_prod(2);
end process;
end arch_multiplier;

 

[amraldo]

Re: vhdl error

Which line generated the error?
--
Amr

 

[FvM]

vhdl error

It's not allowed to place concurrent code (a component instantiation) inside a process.
Consult a VHDL text book or tutorial.

 

[phobos1]

Re: vhdl error

line 49 to 57






vhd(49): (vcom-1144) Value 0 is out of range 3 to 0 (null range).

 

[amraldo]

Re: vhdl error

Check FVM post. It has the clue.
--
Amr

 

[FvM]

Re: vhdl error

I have heard doubts, that some VHDL tools would allow concurrent code inside a process. I was
never aware of such a case, also it's clearly not provided by the language standard.

 

[amraldo]

Re: vhdl error

Actually, I met some tools having bugs in VHDL and C.
So I believe it is possible to happen.
--
Amr