Help me fix my synthesizable Verilog code

[siva_7517]

Re: Verilog question

Hi,

I have already define the size array of the in_buf_re and in_buf_im .

reg signed [bit-1:0] in_buf_re [7:0];
reg signed [bit-1:0] in_buf_im [7:0];


but still having warning in dc.

Regards,
Siva

 

[funster]

Re: Verilog question

using asynchronous reset instead of synchronous reset to have a try.

many things has no obvious reason, you only can try.

best reagrds

Hi,

Below is a partial of my coding. I have a problem from this code. When i do a synthesis in design_compiler i have warning called where:

Information: There are 1 potential problems in your design. Please run 'check_design' for more information. (LINT-99)


VERILOG CODE:


always@(posedge clk)
begin
if(rst)
data_cnt=0;
else
data_cnt=data_cnt+1;
end

always@(posedge clk)
begin
if (rst) begin
out_re=16'h0000;
out_im=16'h0000;
sync_out=1'b0;
end
else

case(data_cnt)


00: begin
in_buf_re[0]=in_re;
in_buf_im[0]=in_im;
sync_out=1'b0;
end

01: begin
in_buf_re[1]=in_re;
in_buf_im[1]=in_im;
sync_out=1'b0;
end

02: begin
in_buf_re[2]=in_re;
in_buf_im[2]=in_im;
sync_out=1'b0;
end

03: begin
in_buf_re[3]=in_re;
in_buf_im[3]=in_im;
sync_out=1'b0;
end

04: begin
in_buf_re[4]=in_re;
in_buf_im[4]=in_im;
sync_out=1'b0;
end

05: begin
in_buf_re[5]=in_re;
in_buf_im[5]=in_im;
sync_out=1'b0;
end

06: begin
in_buf_re[6]=in_re;
in_buf_im[6]=in_im;
sync_out=1'b0;
end

07: begin
in_buf_re[7]=in_re;
in_buf_im[7]=in_im;
sync_out=1'b0;
end

08: begin
out_re = h_re0;
out_im = h_im0;
sync_out=1'b1;
end

09: begin
out_re = h_re1;
out_im = h_im1;
sync_out=1'b0;
end

10: begin
out_re = h_re2;
out_im = h_im2;
sync_out=1'b0;
end

11: begin
out_re = h_re3;
out_im = h_im3;
sync_out=1'b0;
end

12: begin
out_re = h_re4;
out_im = h_im4;
sync_out=1'b0;
end

13: begin
out_re = h_re5;
out_im = h_im5;
sync_out=1'b0;
end

14: begin
out_re = h_re6;
out_im = h_im6;
sync_out=1'b0;
end

15: begin
out_re = h_re7;
out_im = h_im7;
sync_out=1'b0;
end

default: begin
out_re = 16'h????;
out_im = 16'h????;
sync_out=1'b?;
end


endcase
end

is there any problem with the code?