Help me fix my synthesizable Verilog code

[siva_7517]

Hi,

Below is a partial of my coding. I have a problem from this code. When i do a synthesis in design_compiler i have warning called where:

Information: There are 1 potential problems in your design. Please run 'check_design' for more information. (LINT-99)


VERILOG CODE:


always@(posedge clk)
begin
if(rst)
data_cnt=0;
else
data_cnt=data_cnt+1;
end

always@(posedge clk)
begin
if (rst) begin
out_re=16'h0000;
out_im=16'h0000;
sync_out=1'b0;
end
else

case(data_cnt)


00: begin
in_buf_re[0]=in_re;
in_buf_im[0]=in_im;
sync_out=1'b0;
end

01: begin
in_buf_re[1]=in_re;
in_buf_im[1]=in_im;
sync_out=1'b0;
end

02: begin
in_buf_re[2]=in_re;
in_buf_im[2]=in_im;
sync_out=1'b0;
end

03: begin
in_buf_re[3]=in_re;
in_buf_im[3]=in_im;
sync_out=1'b0;
end

04: begin
in_buf_re[4]=in_re;
in_buf_im[4]=in_im;
sync_out=1'b0;
end

05: begin
in_buf_re[5]=in_re;
in_buf_im[5]=in_im;
sync_out=1'b0;
end

06: begin
in_buf_re[6]=in_re;
in_buf_im[6]=in_im;
sync_out=1'b0;
end

07: begin
in_buf_re[7]=in_re;
in_buf_im[7]=in_im;
sync_out=1'b0;
end

08: begin
out_re = h_re0;
out_im = h_im0;
sync_out=1'b1;
end

09: begin
out_re = h_re1;
out_im = h_im1;
sync_out=1'b0;
end

10: begin
out_re = h_re2;
out_im = h_im2;
sync_out=1'b0;
end

11: begin
out_re = h_re3;
out_im = h_im3;
sync_out=1'b0;
end

12: begin
out_re = h_re4;
out_im = h_im4;
sync_out=1'b0;
end

13: begin
out_re = h_re5;
out_im = h_im5;
sync_out=1'b0;
end

14: begin
out_re = h_re6;
out_im = h_im6;
sync_out=1'b0;
end

15: begin
out_re = h_re7;
out_im = h_im7;
sync_out=1'b0;
end

default: begin
out_re = 16'h????;
out_im = 16'h????;
sync_out=1'b?;
end


endcase
end

is there any problem with the code?

 

[dr.farnsworth]

potential simulation-synthesis mismatch if index

You dont need to specify sync_out=1'b0; in every case statement

 

[dcreddy1980]

Re: Verilog question

default: begin
out_re = 16'h????;
out_im = 16'h????;
sync_out=1'b?;
end

u should use only '0' or '1' or 'Z'(for tri-states) for synthesis.....thats the reason for the warning

Regards,
dcreddy

 

[jelydonut]

Re: Verilog question

yah.. what dcreddy said..

never leave unknowns in any default/reset condition as they will affect the simulation/synthesis.. If you don't care about them then don't put them in then case statement..

the main problem is your using "?".. personally i never would use a x or ? in my code.. if you don't care about their state changing, then either x => x; , or don't define it at all as you will already want it to be a registered/latched value (perferably in a seperate always block).. and if you only care about certain bits in the case then define them seperatly (blah[4], !blah[3], blah[0])..

also.. to be safe in your case statement.. define them as binary or hex values..
ie ( 8'h03 : begin) cause the simulator may think decimal the way you wrote it.. i donno though.. never tried writing it your way.. also paste the whole module next time.. incase you inferred a reg accidentally or something...

look around and find the "reuse methodology" manual.. im sure its around : o ) There is a really good couple of chapters on proper syntax/modeling..


jelydonut

 

[nand_gates]

Re: Verilog question

I am sorry to say this. But I think this is not the correct way of writing
synthesizable code. Verilog is HDL means it a language to describe the
digital hardware. While writing RTL you shall think of hardware first and
then use Verilog to just describe it. Go thro' synopsys RTL guidelines first.

 

[siva_7517]

Re: Verilog question

Hi,

thanks for the feedback. I have removed the "default" in the case statement but still having the same problem. But, when i removed the code below then the warning gone:

always@(posedge clk)
begin
if(rst)
data_cnt=0;
else
data_cnt=data_cnt+1;
end

always@(posedge clk)
begin
if (rst) begin
out_re=16'h0000;
out_im=16'h0000;
sync_out=1'b0;
end
else


I think the problem is coming from the if else statement. I think some modification has to been done here. Need some help. thanx

 

[altair_06]

Re: Verilog question

HI,

Removing the default condition won't solve the problem.Default condtion is a must for proper synthesis.Instead of removing the default condition try to replace the unknown values in the default condition by some known values as stated earlier.

 

[snake_eyes]

Re: Verilog question

The First mistake (I am surprised nobody noticed it yet) is that in the clock process you are using asynchronous reset. Hence the asynchronous reset has to be in sensitivity list. The synthesis tool shall give a warning regarding incomplete sensitivity list.

I am going though your code. Shall post the correct code in my next post.

 

[haytham]

Re: Verilog question

Hi
reset signal should be also in the senstivity list of the always statement

Thanks

 

[wangkl]

Verilog question

What a mess!

 

[tom_hanks]

Re: Verilog question

hi,
try this one...

always@(posedge clk)
begin
if(rst)
begin
data_cnt=0;
out_re=16'h0000;
out_im=16'h0000;
sync_out=1'b0;
end
else
begin
data_cnt=data_cnt+1;
case(data_cnt)
....

endcase
end
end


your previous code was runnig parallely..

i guess now your prob is resolve..

 

[chviswanadh]

Re: Verilog question

try to avoid integer data types because they are synthesized to wide buses.
u can use vectors of bits for integers

 

[siva_7517]

Re: Verilog question

Hi,

I try to modify the code as below, but the warning still there:

always@(posedge rst or posedge clk)
begin
if(rst)
data_cnt=0;
else
data_cnt=data_cnt+1;
end

always@(posedge rst or posedge clk)
begin
if (rst) begin
out_re=16'h0000;
out_im=16'h0000;
sync_out=1'b0;
end
else

 

[tom_hanks]

Re: Verilog question

δ
ξ

Hi Siva
HAv u tried the code i hav menstion
§Δ

 

[nand_gates]

Re: Verilog question

Checkout this one! Hope this helps!

always@ (posedge clk) begin
   if(rst)
     data_cnt <= 0;
   else
     data_cnt <= data_cnt + 1;
end

   reg [15:0] out_re_nx;
   reg [15:0] out_im_nx;
   reg        sync_out_nx;
always@ (posedge clk or posedge rst) begin
   if (rst) begin
      out_re <=16'h0000;
      out_im <=16'h0000;
      sync_out <=1'b0;
   end else begin
      out_re <= out_re_nx;
      out_im <= out_im_nx;
      sync_out <= sync_out_nx;
   end
end

reg in_buf_we;
reg [3:0] in_buf_addr;
always@ (posedge clk) begin
   if (in_buf_we) begin
      in_buf_re[in_buf_addr] <= in_re;
      in_buf_im[in_buf_addr] <= in_im;
   end
end
   
always @(/*AS*/data_cnt or h_im0 or h_im1 or h_im2 or h_im3 or h_im4 or h_im5
         or h_im6 or h_im7 or h_re0 or h_re1 or h_re2 or h_re3 or h_re4
         or h_re5 or h_re6 or h_re7 or sync_out) begin
   out_re_nx = out_re;
   out_im_nx = out_im;
   sync_out_nx = sync_out;
   in_buf_addr = 0;
   in_buf_we = 0;
   
   case (data_cnt)
     00: begin
        in_buf_addr = 0;
        in_buf_we = 1;
     end
     
     01: begin
        in_buf_addr = 1;
        in_buf_we = 1;
     end
     
     02: begin
        in_buf_addr = 2;
        in_buf_we = 1;
     end
     
     03: begin
        in_buf_addr = 3;
        in_buf_we = 1;
     end
     
     04: begin
        in_buf_addr = 4;
        in_buf_we = 1;
     end
     
     05: begin
        in_buf_addr = 5;
        in_buf_we = 1;
     end
     
     06: begin
        in_buf_addr = 6;
        in_buf_we = 1;
     end
     
     07: begin
        in_buf_addr = 7;
        in_buf_we = 1;
     end
     
     08: begin
        out_re_nx = h_re0;
        out_im_nx = h_im0;
        sync_out_nx = 1'b1;
     end
       
     09: begin
        out_re_nx = h_re1;
        out_im_nx = h_im1;
     end
     
     10: begin
        out_re = h_re2;
        out_im = h_im2;
     end       
               
     11: begin 
        out_re = h_re3;
        out_im = h_im3;
     end       
               
     12: begin 
        out_re = h_re4;
        out_im = h_im4;
     end       
               
     13: begin 
        out_re = h_re5;
        out_im = h_im5;
     end       
               
     14: begin 
        out_re = h_re6;
        out_im = h_im6;
     end
     
     15: begin
        out_re = h_re7;
        out_im = h_im7;
     end
   endcase
end // always @ (...

 

[xihushui]

Verilog question

use if....else.i think you should use the else when you use if .if you don,the DC will generate a latch.but it don't tihnk the latch is necessary.

 

[siva_7517]

Re: Verilog question

Hi,

I try with the coding that have been send by nand_gates, but there is a width difference on in_buf_re.


always@(posedge clk)
begin
if (in_buf_we)
begin
in_buf_re[in_buf_addr] <= in_re;
in_buf_im[in_buf_addr] <= in_im;
end
end


The warning is stated below:


Warning: /projects/rfid/design/dspuhf/dfII/newdesign/8point/system_fft_synopsys/withoutdft/full_3_2fft.v:106: Potential simulation-synthesis mismatch if index exceeds size of array 'in_buf_re'. (ELAB-349)
Warning: /projects/rfid/design/dspuhf/dfII/newdesign/8point/system_fft_synopsys/withoutdft/full_3_2fft.v:107: Potential simulation-synthesis mismatch if index exceeds size of array 'in_buf_im'. (ELAB-349)

 

[nand_gates]

Re: Verilog question

Here is small correcttion in the code!
Now the errors should go!

reg in_buf_we;
reg [2:0] in_buf_addr;   //  changed 
always@ (posedge clk) begin
   if (in_buf_we) begin
      in_buf_re[in_buf_addr] <= in_re;
      in_buf_im[in_buf_addr] <= in_im;
   end
end

 

[siva_7517]

Re: Verilog question

Hi,

I have already notice the mistake before and have changed it to :
reg [2:0] in_buf_addr

but the warning is still there...

nand_gate, can i get your email address so that i can send u my whole design. Maybe ,U can try to synthesis it. My email is siva_7517@yahoo.com.sg

 

[petrelflying]

Verilog question

HI,siva_7517:
first, you have to define the size of array in_buf_re and in_buf_im

Added after 1 seconds:

HI,siva_7517:
first, you have to define the size of array in_buf_re and in_buf_im