Help me fix my code for checking one bit in one clock (Verilog)

[anandanips]

verilog error check

my code need to check one bit in one clock.next bit in another clock. but it checking ann bits in one pos edge clk. please say correct way


module HighSpeedRouting(clk,res);
input clk;
output[15:0] res;
reg[15:0] res=16'b0;
reg[31:0]addr=32'b00000000000000000000000000011111;
reg[47:0]node1=48'b000000000000000000000000000000000000000000000010;//2
reg[47:0]node2=48'b000000000000000000000000000000010000000000000100;//4
reg[47:0]node3=48'b000000000000000000000000000000100000000000000110;//6
reg[47:0]node4=48'b000000000000000000000000000000110000000000001000;//8
reg[47:0]node5=48'b000000000000000000000000000001000000000000001010;//10
reg[47:0]node6=48'b000000000000000000000000000001010000000000001100;//12
reg[47:0]node7=48'b000000000000000000000000000001100000000000001110;//14
reg[47:0]node8=48'b000000000000000000000000000001110000000000010000;//16
reg[47:0]node9=48'b000000000000000000000000000010000000000000010010;//18
reg[47:0]node10=48'b000000000000000000000000000010010000000000010100;//20
reg[47:0]node11=48'b000000000000000000000000000010100000000000010110;//22
reg[47:0]node12=48'b000000000000000000000000000010110000000000011000;//24
reg[47:0]node13=48'b000000000000000000000000000011000000000000011010;//26
reg[47:0]node14=48'b000000000000000000000000000011010000000000011100;//28
reg[47:0]node15=48'b000000000000000000000000000011100000000000011110;//30
reg[47:0]node16=48'b000000000000000000000000000011110000000000100000;//32
reg[47:0]node17=48'b000000000000000000000000000100000000000000100010;//34
reg[47:0]node18=48'b000000000000000000000000000100010000000000100100;//36
reg[47:0]node19=48'b000000000000000000000000000100100000000000100110;//38
reg[47:0]node20=48'b000000000000000000000000000100110000000000101000;//40
reg[47:0]node21=48'b000000000000000000000000000101000000000000101010;//42
reg[47:0]node22=48'b000000000000000000000000000101010000000000101100;//44
reg[47:0]node23=48'b000000000000000000000000000101100000000000101110;//46
reg[47:0]node24=48'b000000000000000000000000000101110000000000110000;//48
reg[47:0]node25=48'b000000000000000000000000000110000000000000110010;//50
reg[47:0]node26=48'b000000000000000000000000000110010000000000110100;//52
reg[47:0]node27=48'b000000000000000000000000000110100000000000110110;//54
reg[47:0]node28=48'b000000000000000000000000000110110000000000111000;//56
reg[47:0]node29=48'b000000000000000000000000000111000000000000111010;//58
reg[47:0]node30=48'b000000000000000000000000000111010000000000111100;//60
reg[47:0]node31=48'b000000000000000000000000000111100000000000111110;//62
reg[47:0]node32=48'b000000000000000000000000000111110000000001000000;//64


always@(posedge clk)
begin
if(addr[31]==1'b0)
begin
if(addr[30]==1'b0)
begin
if(addr[29]==1'b0)
begin
if(addr[28]==1'b0)
begin
if(addr[27]==1'b0)
begin
if(addr[26]==1'b0)
begin
if(addr[25]==1'b0)
begin
if(addr[24]==1'b0)
begin
if(addr[23]==1'b0)
begin
if(addr[22]==1'b0)
begin
if(addr[21]==1'b0)
begin
if(addr[20]==1'b0)
begin
if(addr[19]==1'b0)
begin
if(addr[18]==1'b0)
begin
if(addr[17]==1'b0)
begin
if(addr[16]==1'b0)
begin
if(addr[15]==1'b0)
begin
if(addr[14]==1'b0)
begin
if(addr[13]==1'b0)
begin
if(addr[12]==1'b0)
begin
if(addr[11]==1'b0)
begin
if(addr[10]==1'b0)
begin
if(addr[9]==1'b0)
begin
if(addr[8]==1'b0)
begin
if(addr[7]==1'b0)
begin
if(addr[6]==1'b0)
begin
if(addr[5]==1'b0)
begin
if(addr[4]==1'b0)
begin
if(addr[3]==1'b0)
begin
if(addr[2]==1'b0)
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node1[15:0];
end
else
begin
res[15:0]<=node2[15:0];
end
end ///////////////////////////////////////////////////
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node3[15:0];
end
else
begin
res[15:0]<=node4[15:0];
end
end
end /////////////////////////////////////////////////
else
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node5[15:0];
end
else
begin
res[15:0]<=node6[15:0];
end
end
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node7[15:0];
end
else
begin
res[15:0]<=node8[15:0];
end
end
end
end///////////////////////////////////////////////////////

else
begin
if(addr[2]==1'b0)
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node9[15:0];
end
else
begin
res[15:0]<=node10[15:0];
end
end///////////////////////////////////////////////////
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node11[15:0];
end
else
begin
res[15:0]<=node12[15:0];
end
end
end /////////////////////////////////////////////////
else
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node13[15:0];
end
else
begin
res[15:0]<=node14[15:0];
end
end
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node15[15:0];
end
else
begin
res[15:0]<=node16[15:0];
end
end
end
end
end///////////////////////////////////////////////////////
else
begin
if(addr[3]==1'b0)
begin
if(addr[2]==1'b0)
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node17[15:0];
end
else
begin
res[15:0]<=node18[15:0];
end
end ///////////////////////////////////////////////////
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node19[15:0];
end
else
begin
res[15:0]<=node20[15:0];
end
end
end /////////////////////////////////////////////////
else
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node21[15:0];
end
else
begin
res[15:0]<=node22[15:0];
end
end
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node23[15:0];
end
else
begin
res[15:0]<=node24[15:0];
end
end
end
end///////////////////////////////////////////////////////

else
begin
if(addr[2]==1'b0)
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node25[15:0];
end
else
begin
res[15:0]<=node26[15:0];
end
end///////////////////////////////////////////////////
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node27[15:0];
end
else
begin
res[15:0]<=node28[15:0];
end
end
end /////////////////////////////////////////////////
else
begin
if(addr[1]==1'b0)
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node29[15:0];
end
else
begin
res[15:0]<=node30[15:0];
end
end
else
begin
if(addr[0]==1'b0)
begin
res[15:0]<=node31[15:0];
end
else
begin
res[15:0]<=node32[15:0];
end
end
end
end
end
end ///////////////////////////////////////////////////////

end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
endmodule

 

[polu]

Re: verilog error check

Your code is written to check all hte bits on a clock edge.
You could write the code something like below....

i =31;
always@(posedge clk)
begin
if(i >= 0 && i<=31 && addr == 0)
i = i - 1;
else
j = i;
end

'J' holds the address value which holds non -zero data.

Rgds,
Kiran Polu