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Help me fix FPGA VHDL code for a multiply accumulator

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Tom2

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hello everyone,
i have written the code beneath in VHDL for a mupltiply accumulator and
while it is coming in FPGA port, the led don't provide with the correct
result. is there anyone who knows what the problem is?



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity olokliro2 is
port (CLK:in std_logic;
Sw0,Sw1,Sw2,Sw3:in std_logic;
Led0,Led1,Led2,Led3:eek:ut std_logic );
end olokliro2;

architecture Behavioral of olokliro2 is


component divider is
Port ( Clock : in STD_LOGIC;
Clock2 : out STD_LOGIC);
end component;

component counterrr
port (
clk: IN std_logic;
ce: IN std_logic;
sinit: IN std_logic;
q_thresh0: OUT std_logic;
q: OUT std_logic_VECTOR(4 downto 0));
end component;


component control is
Port ( clk : in STD_LOGIC;
address: in STD_LOGIC_vector(4 downto 0);
CE : out STD_LOGIC;
FD : out STD_LOGIC;
ND : out STD_LOGIC);
end component;


component memor is
port (
addr: IN std_logic_VECTOR(4 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
en: IN std_logic);
end component;

component mulaccu
port (
A: IN std_logic_VECTOR(15 downto 0);
B: IN std_logic_VECTOR(7 downto 0);
Q: OUT std_logic_VECTOR(28 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
FD: IN std_logic;
ND: IN std_logic;
RDY: OUT std_logic);
end component;

component memori2 is
port (
addr: IN std_logic_VECTOR(4 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic);
end component;



--component or2b is
--PORT (a, b : IN std_logic;
-- c : OUT std_logic);
--end component;



Signal qmul :std_logic_vector(23 downto 0);
Signal AccSm :std_logic_vector(28 downto 0);
Signal qcount: std_logic_vector(4 downto 0);
Signal Switch: std_logic_vector(2 downto 0);
Signal qmemo1 :std_logic_VECTOR(15 downto 0);
SIgnal qmemo2 :std_logic_VECTOR(7 downto 0);
signal redyy,CEAc,ceCoun,FD,RDY,ND,clock: std_logic;

begin

A0: control port map
( clk => clock,
address=>qcount,
CE => CEAc,
FD => FD,
ND => ND
);



A1: divider port map (clk,clock);
A3: memor port map (addr=>qcount,CLK=>clock,dout=>qmemo1,en=>redyy);
A4: memori2 port map (addr=>qCount,CLK=>clock,dout=>qmemo2,en=>redyy);
A6: mulaccu port map (
A => qmemo1,
B => qmemo2,
Q => AccSm,
CLK => clock,
CE => CEAc,
FD => FD,
ND => ND,
RDY => RDY);


A7: counterrr
port map (
clk => clock,
ce => ceCoun,
sinit => Sw1,
q_thresh0 => ceCoun,
q => qcount);


Switch<=Sw3&Sw2&Sw1;


Process(clock,Switch)
begin
case (Switch) is
when "000" =>
Led0<=not clock;
Led1<=not FD;
Led2<=not ND;
Led3<=not RDY;
when "010" =>
Led0<=not AccSm(0);
Led1<=not AccSm(1);
Led2<=not AccSm(2);
Led3<=not AccSm(3);
when "001" =>
Led0<=not AccSm(4);
Led1<=not AccSm(5);
Led2<=not AccSm(6);
Led3<=not AccSm(7);
when "011" =>
Led0<=not AccSm(8);
Led1<=not AccSm(9);
Led2<=not AccSm(10);
Led3<=not AccSm(11);
when "100" =>
Led0<=not AccSm(12);
Led1<=not AccSm(13);
Led2<=not AccSm(14);
Led3<=not AccSm(15);
when "101" =>
Led0<=not AccSm(16);
Led1<=not AccSm(17);
Led2<=not AccSm(18);
Led3<=not AccSm(19);
when "110" =>
Led0<=not AccSm(20);
Led1<=not AccSm(21);
Led2<=not AccSm(22);
Led3<=not AccSm(23);
when OTHERS =>
end case;
end process;








end Behavioral;
 

togarha

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fpga

Hi!

When you have Sw1,Sw2 and Sw3 to 0, the led goes with the clock?

Why you do not make a testbench and post its results?

Regards,
 

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