Help me fix an UART Verilog code

[phobos1]

module TX_fsm(
input clk,
input rst,
input baudclk,
input go,
input [7:0] data,
output reg TX
);

wire cclk;

BUFG UUT4 (.I(clk),.O(cclk));

parameter IDLE = 4'b0000,
START = 4'b0001,
BUSY = 4'b0010,
STOP1 = 4'b0011,
STOP2 = 4'b0100,
DONE = 4'b0101;


reg [3:0]state, next;
reg [7:0]temp;

always@(posedge cclk, negedge rst)
begin
if (!rst) begin
state <= IDLE;
TX <= 1'b0;
end
else
state <= next;
end

always@(state, data)
begin
TX = 1'b0;
next = 4'bx;
case (state)
IDLE : begin
TX = 1'b1;
if (!go)
next = IDLE;
else
next = START;
end
START : begin
if (baudclk)
TX = 1'b0;
temp[7:0] = data[7:0];
next = BUSY;
end
BUSY : begin
if (baudclk)
TX = temp[7];
temp[7:0] = {temp[7:0],1'b0};
if (temp[7:0] == 8'b0)
next = STOP1;
else
next = BUSY;
end
STOP1 : begin
if (baudclk)
TX = 1'b1;
next = STOP2;
end
STOP2 : begin
if (baudclk)
TX = 1'b1;
next = DONE;
end
DONE : next = IDLE;
endcase
end
endmodule

 

[TrickyDicky]

Re: uart help in verilog

and whats the problem?

 

[phobos1]

Re: uart help in verilog

correct me am i right

---------- Post added at 11:57 ---------- Previous post was at 11:57 ----------

i am not getting the data shifted out

---------- Post added at 12:00 ---------- Previous post was at 11:57 ----------

I AM not getting data out at tx i use dcm for 12mhz clk and using it for baud rate generation

 

[rberek]

Re: uart help in verilog

Well, for one thing, you aren't using temp as a register. It is not described in your synchronous block like state is. So it will never be able to store anything. So lines like:

temp[7:0] = {temp[7:0],1'b0};

cannot work as you want them to.


Secondly, you have an incomplete sensitivity list. Though sensitivity lists have not been required at all in combinatorial blocks for many years. Unless you have an ancient simulator/synthesizer, always @ (*) removes the need to remember every signal.

r.b.

 

[mrflibble]

Re: uart help in verilog

Have you tried putting this in a testbench yet? If so, do you have a screenshot of the signals?

That, and personally I'd use non-blocking assignments like this:

    temp[7:0] <= {temp[7:0],1'b0};

PS: you can put the [ code] tag around your code, that makes it a bit more readible. Especially if you use space for indentation (not tab). That makes it easier for other people to verify your code.

 

[phobos1]

Re: uart help in verilog

module TX_fsm(
input clk,
input rst,
input baudclk,
input go,
input [7:0] data,
output reg TX,
output reg FIN
);

wire cclk;

BUFG UUT4 (.I(clk),.O(cclk));

parameter IDLE = 4'b0000,
START = 4'b0001,
BUSY = 4'b0010,
STOP1 = 4'b0011,
STOP2 = 4'b0100,
DONE = 4'b0101;


reg [3:0]state, next;
reg [7:0]temp,temp_reg;
reg [3:0]i,i_reg;


always@(posedge cclk, posedge rst)
begin
if (rst)
begin
state <= IDLE;
temp <= 8'd0;
i <= 4'd0;
end
else
begin
state <= next;
temp <= temp_reg;
i <= i_reg;
end
end

always@*
begin
TX = 1'b0;
FIN = 1'b0;
next = 4'bx;
temp_reg = 8'd0;
i_reg = 4'd0;
case (state)
IDLE : begin
TX = 1'b1;
if (!go)
next = IDLE;
else
next = START;
end
START : begin
FIN = 1'b0;
if (baudclk)
TX = 1'b0;
temp_reg[7:0] = data[7:0];
next = BUSY;
end
BUSY : begin
if (baudclk)
TX = temp[7];
temp_reg[7:0] = {temp[7:0],1'b0};
i_reg = i[3:0] + 1'b1;
if (i[3:0] == 4'd8)
next = STOP1;
else
next = BUSY;
end
STOP1 : begin
i_reg = 4'd0;
if (baudclk)
TX = 1'b1;
next = STOP2;
end
STOP2 : begin
if (baudclk)
TX = 1'b1;
next = DONE;
end
DONE : begin
next = IDLE;
FIN = 1'b1;
end
endcase
end
endmodule


some one help me regarding baudclk and i have corrected my previous errors also added my screenshot...........................