Help me find the error in this code for generating clock pulse at lower frequency

hi ! can anyone help i could not find the error in this code. i need to generate clock pulse at lower frequency .
entity clkgen is
Port ( clk: in STD_LOGIC;
clk1: out std_logic;
c1: out std_logic_vector( 5 downto 0);
reset:in std_logic);
end clkgen;

architecture Behavioral of clkgen is
--signal c2: std_logic_vector( 5 downto 0):="000000";
--signal clk2:std_logic:='0';
begin
process(clk,reset)
variable c2:std_logic_vector( 5 downto 0);
variable clk2: std_logic;
begin

if(clk'event and clk = '1') then
if (reset='1')then
c2:="110010";
clk2:='0';
end if;
else if (c2>"000000") then
c2:=c2-1;
end if;
if(c2="000000") then
clk2:=not(clk2);
c2:="110010";
end if;


c1<=c2;
clk1<=clk2; end if;
end process;
end Behavioral;