Help me design filter for PLL having as reference 500 Mhz clock and 8GHz output

[mouzid]

Dear friends,
I need you help for the design of a Filter for a PLL having as refernce clock 500 Mhz and an output of 8 Ghz.
The filter will be inserted between the CP and the VCO already designed.
Please help.

 

[AdvaRes]

pll filter design

I need also to know more about this issue.
Any papers, book discussing this ?

 

[mouzid]

pll filter für 8ghz

Is my question difficult ?
Please help !

 

[nandu]

pll filter design

First of all you need decide if you want to use an active or a passive filter. Lets say you design the simpler of the two which is a passive filter. Now you must decide on the bandwidth of your PLL (which is the frequency on the bode plot where the loop gain of the PLL crosses 0db). The bandwidth must be less than 10% of your reference signal of 500MHz. Usually it is about 1% or even less. A lesser bandwidth causes longer lock times but smaller reference feedthrough to the output and also lesser noise from the reference source.

Since you are using a charge pump, yours must be a 2nd order PLL having 2 integrators in the loop (the CP and VCO). So you need to introduce a zero to make the loop stable. The simplest way is to have a resistor in parallel with the capacitor of the loop filter. The zero must be placed in such a way that you have a large damping factor (4 or more maybe).

So you see the loop filter in a PLL determines the entire loop dynamics. It is difficult to compress all of it into a single mesage. I'd suggest you to go through some book before jumping into the design.

 

[wilwal]

Re: PLL's Filter Design

As PLL designer,i will suggest you use software to design your loop filter,instead of getting into alot mathematics(especially Laplace transforms) and control theory.Some of the software you may use depends on your min and max frequency of the loop.One that i found easy to use is ADI simPLL(where you can enter all parameters of the VCO and other componets within the PLL) or one by national semiconductors.I suggest as a practical engineer depending on your VCO tuning voltage,you may need a passive or active loop filter.

If you are intersted in details of PLL i will suggest the following resources:
1.Phase lock basics: William F.Egan
2.Frequency synthesis by phase lock: William Egan: publisher Wiley
3.Some excellent white papers on PLL design on Analog devices website.

Also i was intersted to know if you are designing each component within the PLL by yourself or you are using third party componets?

Added after 51 minutes:

By the way all this softwares are free to download.I especially encourage you to use the ADI one if you are using Analog devices synthesizers.Downlod it andd look at the help section where you can find alot of technical materials on loop filters and types.All the best

 

[nandu]

PLL's Filter Design

@Mouzid
There was an error in my previous message. To get a zero you need to have the charge pump driving a series combination of resistor and capacitor and not a parallel combination as I had mentioned.

 

[mouzid]

PLL's Filter Design

Thanks for your elaborated replies. Could you please upload documentations regarding this issue ?

 

[wilwal]

Re: PLL's Filter Design

I cant upload materials i have on PLL.I am a new member and i need a way to get out of this.Mauzid get me your email and i will send to you directly.

 

[jecyhale]

Re: PLL's Filter Design

Dear friends,
I need you help for the design of a Filter for a PLL having as refernce clock 500 Mhz and an output of 8 Ghz.
The filter will be inserted between the CP and the VCO already designed.
Please help.

You should give the current of CP, Kvco, Bandwidth you wanted except Fref.

 

[dfrndez]

Re: PLL's Filter Design

Another good resource is "CMOS PLL Synthesizers: Analysis and Design" by Sinencio. The filter is not very trivial. You should read some basic texts at the least like Razavi's (Design and Analysis of CMOS Analog Circuits) book, there will always be tradeoff between the stability of the fliter and the control line ripple (or acquisition range). Accordingly you need to first know the phase margin you want for the PLL and you can simulate the behavior using MATLAB and the equations for the open loop gain in Razavi's.