Help me design an op-amp for an integrator circuit in 12-bit ADC

[firsttimedesigning]

I am trying to design an op-amp that is going to be used in an integrator circuit.
High accuracy is what i am aiminig for in here. Eventually, this integrator circuit will be used in a 12-bit ADC.
I have designed a telescopic op-amp, however the output is not accurate enough. it is off 1mV of the actual result. The gain of the Op-amp is about 75dB and the phase margin is about 50 degrees.
Please give me some advice. Thank you.

 

[Siniša]

miller integrator

offset, input and capacitor leakage?

 

[Vamsi Mocherla]

integrator op amp

Firstly, I am assuming that the OPamp is used for a pipelined or a subranging architecture. Hence, you have to charge a switched capacitor or a resistor at the load. So, the settling will be very important. Any non-linearity in settling will add to distortion reducing the SNDR. A 50 degree phase margin with the actual load is acceptable. Offset is not a big issue because it can be digitally corrected. Gain is not an issue if you are converting less than 6 bits at every stage.

 

[firsttimedesigning]

integrator circuit op amp

Thank you for replying.

Sinisa: offset is about 60uV. input is 0.5V. the resistor in the integrator is 32M and the capacitor is about 31.25fF. Capactior leakage...i have no idea what it is...

Vamsi: Actually I am going to use this in integrating ADC. So, 1 stage and it will convert 12 bits. But yes, settling time is very important. It is one of the resaons why the output of the circuit is not accurate enough.

the op-amp is as follows:

 

[Siniša]

op amp integrator amplifier

Well, 1mV/32MΩ=31.25ρA . You could have that much leakage easy. I would say 32MΩ is to high. Increase capacitance and reduce resistor.

 

[firsttimedesigning]

op-amp integrator -circuit-fantasia.com

Thank you for the reply.
Actually, I started with R = 500k and C = 1p but the result was off by 20mV. As I increase R and decrease C, the result becomes more accurate (1mV). I believe this has to do with the "settling time" of the opamp. When the opamp receives a step input, it will need some time to get to the correct output. The settling time is what i need to minimize in here. And decreasing C helps however, 31.25fF is pretty small. The smallest cap that I can make using the technology that I am using is 15fF.
If there is any other suggestion that you can think of, please tell me. Thanks a lot.

 

[gpwu]

op-amp integrator

Try pumps more current to increase BW.

 

[johnyaya]

miller effect in integrator of op-amp

I know this isn't quite what you are looking for, but check out this document from Burr-Brown (now TI) about their dual switched integrator at:
https://www.ti.com/lit/gpn/acf2101
They discuss various errors sources and performance. Maybe it will give you some ideas.

 

[pabloec]

integrator op am

this may sound stupid but have you tryed the miller integrator?

 

[royayeboodan]

opamp integrator

This problem occure when output dc voltage and input dc voltage are not similar.example output dc voltage is 0.6 but input dc voltage is 0.this create error in feedback.for resolve this problem,you must set output dc voltage and input dc voltage ,similar.
second way is that use four clock that two clock have delay ratio to other two click.
good luck

 

[CherryQ]

op amp integrator phase

this may sound stupid but have you tryed the miller integrator?

Do you mean GmC-OTA as the Miller integrator? Thanks.

 

[rokibulalam]

operational amplifier integrator

I am trying to design an op-amp that is going to be used in an integrator circuit.
High accuracy is what i am aiminig for in here. Eventually, this integrator circuit will be used in a 12-bit ADC.
I have designed a telescopic op-amp, however the output is not accurate enough. it is off 1mV of the actual result. The gain of the Op-amp is about 75dB and the phase margin is about 50 degrees.
Please give me some advice. Thank you.

Have u tried to minimize the load effect?

 

[gpwu]

accuracy integrator circuit

1. increase tail I to increase BW
2. reduce parasitic caps to increase feedback factor

 

[wateror]

miller integrator op amp

why not try two stage?

 

[northeast1]

opamp integrator design

I am trying to design an op-amp that is going to be used in an integrator circuit.
High accuracy is what i am aiminig for in here. Eventually, this integrator circuit will be used in a 12-bit ADC.
I have designed a telescopic op-amp, however the output is not accurate enough. it is off 1mV of the actual result. The gain of the Op-amp is about 75dB and the phase margin is about 50 degrees.
Please give me some advice. Thank you.

You should think about the settling time and slew rate.