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Help me design a schematic diagram of Dwell Timer

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Aug 17, 2001
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timer shematic

Hi all

The below picture represent a block diagram of a DWELL TIMER.

Does anybody know how to design the shematic diagram.(connections)

The two D-type flip-flop(4013)are used as edge triggerning device which activate the monostable that it turn activates the astable.

Please HELP !!!!!!
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dwell timer

I notice that the input to your dwell timer comes from a temperature controler. A dwell timer ( as used in the automobile industry ) makes a simple measurment of how long the points on a car remain open for, the scale is normally in degreas.


Basically the above diagram is a part of controlling a temperature cycling of an enviromental chamber.

In a temperature cucling a dwell time must be present at both the upper and lower temperature limits, know as the upper dwell time and the llower dwell time.
These dwell timer are based on the stabilisation time of the componnet or unit under test, usually in the range of 5 to 25 minuts.

Bsically the block diagram will produce/contoll the below waveform
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Big Hi savvasn
I built one that worked
really well using Phase locked
loop to control a meter, eitherway
it is a good approch.
if interesated ill find the schematic
and forward. let know?

Hi Savvasn

Hope that the schematic diagram will help you a little bit.
Some comments on it:
- R2, R3, R4 are involved in setting of upper and lower temperature limits
- the two D flip-flop are edge thriggered every time when the output voltage of LM35 goes
inside out of the window comparator.
- You will be able to control independent devices: warm and freeze with two relay RL1 and RL2.
obvious the dwell time as well (RV1 and RV2)
- with K1 or K2 you can start either warm or freeze by default as first temperature cycle
- R10, R11, D3, C2, U3:B reset the D flip-flop at the end of each cycle
- the 555 astable from your block diagram was removed because is useless.
You can't predict the slope due to the different thermal gradient dT/dt.
The system goes in infinite loop and the new temperature cycle is started soon as the
environmental chamber hit either upper or lower limit.
However, you can place additional counter in order to set the number of temperature cycling.
- you can replace the pairs : D2-D7, D1-D6, D4-D5 with AND gates
- If I well understand the dwell time required is in the range 5 to 25 minutes.
You will not succeed easy with old genuine 555 without additional components.
Maybe with CMOS variant. However you will need capacitors with low current leakage and big resistor.
For old 555 the input Bias curent is 250nA.
It's true that durind capacitor charging the input comparator transistors are cut off.
But you still need 250nA when the 555 output change status.
Thus, at that moment the required current through the charging resistor must be greater.
The m@ximum value allowed for resistor is (Vcc-0,66Vcc)/Ibias = 20M.
One solution is to use a capacitance multiplier. The R16, R17, R18 and U6 are in charge for that.
With this circuit, the 555 seen an equivalent capacitor C3 multiplied with the ratio of R18/R17.
Thus, for the diagram values the monostable constant is T=100 x 1,1 x RV1 x C3.
I'm confident you understand how easy is doing long delays with microcontrollers.
Nevertheless, the easiest control of the system (threshold values for window comparator, dwell time ...)
Would you think it will be much easier to use a micro with ADC inside and work with numbers instead analog voltage.


I forgot the file:
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