Help me debug a VHDL code for 74381

[mobile-it]

Hi all,

I am starting with learning VHDL in my free time. As an exercise I try to create VHDL code for 74381 serie but I have problems with summation of vectors, can anyone debug and help me further with this small exercise?

Thank you very much

Here is the code:

library IEEE;
use IEEE.std_logic_1164.all;
use work.all;

entity IC74S381 is port(
A: in std_logic_vector (3 downto 0);
B: in std_logic_vector (3 downto 0);
S: in std_logic_vector (2 downto 0);
Cn: in std_logic;
F: out std_logic_vector(3 downto 0);
notP: out std_logic;
notG: out std_logic);
end entity;

architecture behav of IC74S381 is
-- S: 0 0 0 for clear operation
-- S: 0 0 1 B minus A
-- S: 0 1 0 A minus B
-- S: 0 1 1 A plus B
-- S: 1 0 0 (notA and B) or (A and not B)
-- S: 1 0 1 A or B
-- S: 1 1 0 A and B
-- S: 1 1 1 preset
signal Csignal: std_logic_vector (4 downto 0);
begin
process(A,B,S,Cn)
begin
Csignal(0)<=Cn;
case S is
when "000" =>
F<="0000";
when "001" =>
Csignal<=B - A;
when "010" =>
Csignal<=A - B;
when "011" =>
Csignal<= A + B;
when "100" =>
Csignal<= (((not A) and B) or (A and (not B)));
when "101" =>
Csignal <=A or B;
when "110" =>
Csignal<=A and B;
when "111" =>
Csignal<="11111";
end case;
F<=Csignal;
end process;
end behav;

 

[khaila]

Re: 74381

1. you should use " use ieee.std_logic_arith.all; "
2. I don't sure butI think in VHDL you should not drive outputs directlly from PROCESS. You may generate temporal signal to be driven in the process then that signal will drive the output while the statement should be applied out of PROCESS. This is what you did with S.
3. F[3..0] is driven by Csignal[4..0] the width of both are not the same.

My suggest to you:
You should follow carefully after the errors/warnings that the complier produces. Mostlly that errors and /warnings are so clear.

Ths is the best way to learn more.

 

[Iouri]

74381

you might want to get rid of case statement instead use something like that

F<= "0000" when S ="000" else
b-A when S = "0001" else....