Help me convert this to VHDL.

[kokei74]

Hello Guys

I need a help with full operational in VHDL that can execute this matrix multiplier.

This is a 4x4 matrix multiplier i try to make. It has 3-level of step which is :

1st lvl - data write in Ram A and Ram B

2nd lvl - result from multiplication will be stored in temp A,B,C,D

3rd lvl - result from multiplication in temp A,B,C,D will be added together to form 1 element in resulted matrix.

This is hardware implementation of this matrix multiplier.

 

[radix]

Just out of curiousity, how wide is the data?

Also, what is the expectation as to how long the processing should take?

As a rough approximation are you assuming 16 clock cycles to load rams A and B and 4 * 16 clock cycles to do the calcuations? This would give you roughly 80 clock ticks to perfom the calculation. Is that in the range you were thinking?

Radix

 

[kokei74]

Yes as for this diagram the data is 4bit.

the priority for this project is to get the result 1st so i didt put an expectation on how long it takes to complete the multiplication. But yes, as u calculated roughly it would take 80 clock tick to perform the calculation.