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Help me check for the errors in this vhdl code

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sampiper

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Please help me check this PID algorithm code, it complains of errors which have not been able to fix



Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity pid is
    
    port
    (
        -- Input ports
        Clk : in  std_logic;
        reset   : in  std_logic;
        e_in       : in signed  ((DATA_WIDTH-15) downto 0);
        setpoint    : in signed  ((DATA_WIDTH-15) downto 0);
        variable k0 : std_logic_vector(15 downto 0);
        variable k1 : std_logic_vector(15 downto 0);
        variable k2 : std_logic_vector(15 downto 0);
        -- Output ports
        U_out   : out signed;  ((DATA_WIDTH-15) downto 0);
        
            );
end pid;
architecture Behavioral of pid is
 
component DFF is 
   port(
      Q : out signed(15 downto 0);      --output connected to the adder
      Clk :in std_logic;      -- Clock input
      D :in  signed(15 downto 0)      -- Data input from the MCM block.
   );
end component;
 
--read from ADC value
 y <= ADC :in  signed(15 downto 0);
 
 e_in <= setpoint - y
-- Initializations of parameters
signal MCM0,MCM1,MCM2,add_out: signed(15 downto 0);
signal Q1,Q2,Q3 : signed(15 downto 0);
 
-- latching of signals using D flipflop to introduce delay
begin
dff1 : DFF port map(Q1,Clk,U_out);
dff2 : DFF port map(Q2,Clk,e_in);
dff3 : DFF port map(Q3,Clk,e_in);
end
-- storing outputs of the D flipflops
U_prev <= Q1
e_prev(1) <= Q2;
e_prev(2) <= Q3;
 
--Multiple constant multiplications.
MCM0 <= k0*e_in;
MCM1 <= k1*e_prev(1);
MCM2 <= k2*e_prev(2);
 
--adders
add_out1 <= MCM0 + MCM1;
add_out2 <= add_out1 + MCM2;
U_out <= U_prev + add_out2
 
--an output produced at every positive edge of clock cycle.
process
begin
    if(rising_edge(Clk)) then
       
if <reset == 1> then
    u_prev <= 0; 
    e_prev[1] <= 0; 
    e_prev[2] <= 0;
       
else
    e_prev[2] <= e_prev[1]; 
    e_prev[1] <= e_in; 
    u_prev <= u_out; 
end if;
end if;
 
end process;
end Behavioral;
 
--VHDL code for the component DFF is given below:
LIBRARY altera; 
 
USE altera.altera_primitives_components.all; 
 
entity DFF is
begin 
   port(
      Q : out signed(15 downto 0);      --output connected to the adder
      Clk :in std_logic;      -- Clock input
      D :in  signed(15 downto 0)      -- Data input from the MCM block.
   );
end DFF;
 
architecture Behavioral of DFF is 
 
signal qt : signed(15 downto 0) := (others => '0');
 
begin 
 
Q <= qt;
 
process(Clk) 
begin 
  if ( rising_edge(Clk) ) then 
    qt <= D;
  end if;       
end process; 
 
end Behavioral;




The errors it gave are these:
Code:
Error (10500): VHDL syntax error at pid.vhd(18) near text "(";  expecting an identifier, or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at pid.vhd(30) near text "component";  expecting ";", or an identifier ("component" is a reserved keyword), or "entity"
Error (10500): VHDL syntax error at pid.vhd(47) near text "<=";  expecting ";"
Error (10396): VHDL syntax error at pid.vhd(79): name used in construct must match previously specified name "pid"
Error (10523): Ignored construct pid at pid.vhd(5) due to previous errors
Error (10500): VHDL syntax error at pid.vhd(88) near text "port";  expecting "end"
Error (10523): Ignored construct DFF at pid.vhd(86) due to previous errors
 
Last edited by a moderator:

These are essentially trivial syntax errors. They must be resolved top-down, otherwise pseudo errors may be generated as follow-up.

You need to look sharp. Start with extra semicolon in line 18.
 

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