Help me change my job !

[Tan]

Hi,
I am a VLSI Design Engineer.I do only programming on VHDL.Apart from from this i have knowledge on fpga and digital and little bit of verilog.Please let me know if anything is nedded to study for an interview.I am not confident in testbench.However i can manage writing.
Please guide me to change my job.
Thank you.

 

[mmarco76]

Please suggest!!

Imo you should never study for an interview..
I mean an interview is intend to evaluate your knowledges and after that you've to remember that once you've be taken there is a try period in which each part could go away without reasons.
Usually it doesn't happen, but the only reason I can think it shall is if any of the 2 parts has lied in the interview..

So don't study, your knowledge is to be evaluated and often sincerity is appreciate (to me it happens to tell in an interview that somethink was totally foreign to my knowledge and they told me that is ok, because it's a very specialistic things of an application).

Only thing I can suggest is to have an idea of what make the industry to where you're doing the interview, because it's important that you like it.

 

[jdtoronto]

Re: Please suggest!!

Maybe rather than just studying you should get some real learning? Get an FPGA development board, download the appropriate tool-chain and try writing a test-bench! Then you WILL know how to do it.

JD

 

[Tan]

Re: Please suggest!!

thank you so much for your replies.however to face the interview we should have some practise right.without that how can i go and answer questions?

 

[mmarco76]

Please suggest!!

Ah sorry I thought that you've done all that jdtoronto has suggested you.
It's the minimum in digital, more than that you've to understand timing constraint and how to direct your syntesis tool in order to taking that in account (and it's not all time simple expecially if you've more clock domain).