Help me build verification environment for sdram controller

[aswin123]

hi,

i am working on verification of sdram controller.

i don't have good material.

can anybody send specification documents or verification code if available.

and also suggest me how to build verification environment.

thanks.

 

[pintuinvlsi]

sdram controller

Verification Enviroment will depend on HVL you are using for verification
In any verification enviroment you require generator, transmitter, receiver and data checker. You have to include these items in verification enviroment. Also you have to include you design and memory model. Implementation depends on HVL used and specification of controller being tested.

Hopes this will help,

Regards

 

[aswin123]

Re: sdram controller

hi,

thanks for u r reply regarding sdram controller.

i have some more doubts?

can u explain in systemverilog verification point of u/

what is the interface in sdram/

and how to interact with environment.

 

[vishalvartak]

Re: sdram controller

U can read the book on AVM cookbook. Its freely available on Mentor Graphic site along with sample code in SystemVerilog and SystemC
U will require to implement Stimulus_generator, Driver, Monitor, Coverage Collector and ScoreBoard. The sample code to implement these in System Verilog are available in the book

 

[sekapr]

Re: sdram controller

check in opencores.org