------------------------------------------------------------------------------
Begin simulating test protocol procedures...
Warning: Rule S30 (unstable RAM during test procedure operation) was violated 1 times.
Test protocol simulation completed, CPU time=0.00 sec.
------------------------------------------------------------------------------
Begin scan chain operation checking...
Chain c0 successfully traced with 42 scan_cells.
Warning: Rule S19 (nonscan cell disturb) was violated 8 times.
Scan chain operation checking completed, CPU time=0.00 sec.
------------------------------------------------------------------------------
Begin clock rules checking...
Clock rules checking completed, CPU time=0.00 sec.
------------------------------------------------------------------------------
Begin nonscan rules checking...
RAM summary: #RAMS=1, #clock_unstable=0, #load_unstable=1, #read_only=0.
Nonscan cell summary: #DFF=0 #DLAT=0 #RAM_outs=8 tla_usage_type=none
Nonscan rules checking completed, CPU time=0.00 sec.
------------------------------------------------------------------------------
Begin DRC dependent learning...
Fast-sequential depth results: control=2(957), observe=2(392), detect=2(957), CPU time=0.01 sec
DRC dependent learning completed, CPU time=0.01 sec.
------------------------------------------------------------------------------
DRC Summary Report
------------------------------------------------------------------------------
Warning: Rule V14 (missing state) was violated 2 times.
Warning: Rule S19 (nonscan cell disturb) was violated 8 times.
Warning: Rule S30 (unstable RAM during test procedure operation) was violated 1 times.
There were 11 violations that occurred during DRC process.
Design rules checking was successful, total CPU time=0.01 sec.
------------------------------------------------------------------------------
set faults -model transition -atpg_effe -fault_cover
Warning: Unused gate deletion affects fault coverage calculation. (M245)
remove faults -all
0 faults were removed from the fault list.
add fault I1/A[0]
2 faults were added to fault list.
add fault I1/A[1]
2 faults were added to fault list.
add fault I1/A[2]
2 faults were added to fault list.
add fault I1/A[3]
2 faults were added to fault list.
add fault I1/A[4]
2 faults were added to fault list.
add fault I1/A[5]
2 faults were added to fault list.
add fault I1/A[6]
2 faults were added to fault list.
add fault I1/A[7]
2 faults were added to fault list.
add fault I1/D[0]
2 faults were added to fault list.
add fault I1/D[1]
2 faults were added to fault list.
add fault I1/D[2]
2 faults were added to fault list.
add fault I1/D[3]
2 faults were added to fault list.
add fault I1/D[4]
2 faults were added to fault list.
add fault I1/D[5]
2 faults were added to fault list.
add fault I1/D[6]
2 faults were added to fault list.
add fault I1/D[7]
2 faults were added to fault list.
run atpg
##############################
ERROR HERE
##############################
Error: There are no active faults in the fault list. (M114)
Uncollapsed Transition Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 0
Possibly detected PT 0
Undetectable UD 0
ATPG untestable AU 32
Not detected ND 0
-----------------------------------------------
total faults 32
test coverage 0.00%
fault coverage 0.00%
ATPG effectiveness 100.00%
-----------------------------------------------
Pattern Summary Report
-----------------------------------------------
#internal patterns 0
-----------------------------------------------