Help me ! (about switched capacitor amp design)

[lilac]

using class ab switched capacitor

In order to design a switched capacitor amplifier with gain 10, sampling frequency 10MHz.
1) How to decide the specs of it's inner opamp? (Such as unity-gain frequency, slew-rate, etc. )
2) Which kind of opamp can easily be designed to match this request. (class? fold-cascode? or others).
Now I use a class-A opamp with 80dB, 350Mhz unity-gain frequency, but it seems can not work well. The sin waveform was input, after sampling and hold, a triangle waveform is found at output side. Who can give me some idea about it? thanks a lot!

 

[Vamsi Mocherla]

capacitive amplifier

Hey, for a sampling rate of 10 MHz, you would need an amplifier of GBW of about 30-50 MHz. It will take care of settling time. The architecture could be anything. But what is critical is the slew rate of the amplifier. Your amplifier should slew the signal to the capacitors in one phase of the clock. take care of the slew rate spec. Sometimes people confuse the GBW with Slew rate spec. You can have a very huge GBW but if the slew rate is bad, the output will not rise in the rquired time.

Say for a 10 MHz signal, the signal needs to be sampled every 0.1us. So, your slewing current should be able to charge the caps in 1/10 of that time.

 

[avinash]

ota bandwidth switched-capacitor

what should be the gain of opamp

 

[willyboy19]

capacitor thermal noise

The DC gain of the opamp really depends on two things: the required close-loop gain accuracy and the linearity of the switched-capacitor gain stage. If you need 90dB linearity spec for this gain stage, the DC gain of the internal OTA would be at least 20*log10(10) + 90 = 110 dB.

The triangle output of your gain stge is a triangle, in stead of the sinewave shape indicates that you have a very strong odd-order harmonic distortions. That means your settling accuracy is very bad, probably limited by the slew rate of your inner OTA.

There should be plenty of treatment as to how to design an OPAMP with capacitive load in an SC circuitry. The most popular architecture for this OPAMP would be folded-cascode or telescopic amplifier. Don't use a class AB output driver stage if you only have pure capacitive loading.

You need also pay attention to your amplifier's noise performance and make sure the noise bandwidth is well controlled so that the alias of the noise does not become too significant. This will put an upper limit on your GBW of the OTA.

 

[opamp741]

gbw and rise time of an amplifier

i feel that the top level specs r still not very much clear..do u hav any error specs with u..

 

[ezt]

unity gain switched capacitor clock

Hi.
I agree with opamp741. what is the ess (error) specification of your circuit. or you should at least give some information about the Noise performance (SNR) and etc.
I think your specifications are not enough. the required gain of your opamp depends on the topology you have chosen and ess (steady state error).

Regards,
EZT

 

[lilac]

switching capacitor amplifier

Thanks a lot! But I am still confused with it. I think maybe the sampling freqency is too high to my circuit. because for 2MHz sampling frequency, the output waveform is normal . But how to do to make it work at 10MHz sampling frequency?
The spec. of inner opamp I used:
Class-A two-stage Opamp
80dB DC gain;
350Mhz unity-gain frequency;
PM=60;
SR=400V/us.
VDD=3.3V. for 10 DC gain of amplifier, the input signal Vpp=0.2V
I don't know how to do next step. maybe the SR is still not enough, or maybe I should try other topology, such as folded cascode opamp. But before that, I think I 'd better find the reason.
Who can give me any advice or recommend any book I can refer to?

 

[Vamsi Mocherla]

sine wave is too fast for capacitors?

Do not go for very high UGB. I see that you are using a 350 MHz opamp for running 10 MHz frequencies. The thermal noise will be very high in that case. So, do not do a overkill in your UGB. Also there will be a power loss for running at very high frequencies. You can get a rough estimate on the slew rate requirement by measuring your output voltage swing. Say if it is 1Vp-p and a 1 MHz sinewave, then your slew rate requirement says that, you should be able to charge a 1 V in 1/4 time period of your sine wave. So, your slew rate requirement would be about 4 V/µs. For safety we would make it 10 V/µs.

In case of sampled data systems. If you have a 1 MHz sinewave input and a 10 MHz clock, then, you will have 10 samples per wave. But a sinewave slews really fast at the zero crossing point(or common mode level) and changes slowly at the peaks. So as per that calculation, you should see the slew rate of input sinewave at the zero crossing point. Then, you can see the time required for that change. It will give you an estimate of the output slewing. Mostly if you have a slew rate of 10 -15 V/µs, you should not have a problem.

 

[lilac]

how to decide gbw of ota

Thank you Vamsi!
As we known, when apply a large signal to the opamp, for example 1Vpp, one of the input transistor of opamp turns off, the other is still on, so the slew rate SR=Iss/Cc.
But for an amplifier, we also want to get a voltage gain (Vout/Vin). For exampe gain=10, that means for a 2Vpp output, the input signal is only 0.2Vpp. this situation is different with gain=1, the slew rate at this situation should be higher in order to meet the request.
Now the compensation capacitance I used is 500ff, the tail current is 200us. but the SR(400V/us) seems still not enough to work at 10MHz sampling frequency(T=100ns). How should I do? It seems a little difficult to go on increasing the tail current.

 

[opamp741]

If u assume a 0.4% error at the o/p of amp [input reffered will be 0.04%<-good enough value]
ur Gain req will be 75dB and Wcl will be 20MHz [UGB 220MHz]..
and the phase margin shd be close to 72 degree "at Wcl" (forget abt PM at UGB)

read this paper to know whether ur amp is slew rate limited or UGB limited..

Plz click "helped me" button if i really helped u..

Good Luck

 

[opamp741]

Ur first stage current requirments will be:

UGB perspective: Ib1 = Gm * Von/2 = 11Meg * Cc
SR Perspective: Ib1 = 8 Vf fs=160Meg* Cc

 

[hebu]

Wa! As you guys can see, we need to increase the current of Ib to meet the
SR requirement. How do we know we don't overkill the SR specification?

 

[hebu]

The DC gain of the opamp really depends on two things: the required close-loop gain accuracy and the linearity of the switched-capacitor gain stage. If you need 90dB linearity spec for this gain stage, the DC gain of the internal OTA would be at least 20*log10(10) + 90 = 110 dB.

The triangle output of your gain stge is a triangle, in stead of the sinewave shape indicates that you have a very strong odd-order harmonic distortions. That means your settling accuracy is very bad, probably limited by the slew rate of your inner OTA.

There should be plenty of treatment as to how to design an OPAMP with capacitive load in an SC circuitry. The most popular architecture for this OPAMP would be folded-cascode or telescopic amplifier. Don't use a class AB output driver stage if you only have pure capacitive loading.

You need also pay attention to your amplifier's noise performance and make sure the noise bandwidth is well controlled so that the alias of the noise does not become too significant. This will put an upper limit on your GBW of the OTA.

I can't realize how we get this spec 20*log10(10) + 90 = 110 dB?
1)The linearity means the THD?
2)Why log10(10)? Is it a rule of thumb?