Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help in writing Verilog code for t flipflop with asynchronous Load.

Status
Not open for further replies.

maxxtorr723

Newbie level 5
Joined
Oct 19, 2013
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
64
Hi, I am designing a jitter bounded DPLL in verilog for which I need a T flip-flop (for a down counter) which can toggle output on positive edge and load data asynchronously on negative edge. I wrote the code but it is not working as needed. Code is :-

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
module tff_async_load (
data  , // Data Input
clk   , // Clock Input
load , // Reset input
q       // Q output
);
//-----------Input Ports---------------
input data, clk, load ; 
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk or negedge load)
if (~load) begin
  q <= data;
end else
 begin
  q <= !q;
end
 
endmodule //End Of Module tff_async_reset


The problem in this program is that even though the always@ block is activated at negative edge but since it checks if load=0 so say in case load is still at 0 and positive edge of clk arrives and the logic then checks to find that load=0 and again loads the data to q.
I am unable to figure out how to make this loading of data as edge triggered.
Please help!
 

ads-ee

Super Moderator
Staff member
Joined
Sep 10, 2013
Messages
7,854
Helped
1,815
Reputation
3,640
Reaction score
1,780
Trophy points
1,393
Location
USA
Activity points
59,348
What you are trying to describe is not a flip-flop that exists. There aren't any rising edge clocked, falling edge load registers in an FPGA.

You could do something hideous like this:

Code Verilog - [expand]
1
2
3
4
5
6
7
8
always @ (negedge clk)
  load_dly <= load;
 
assign load_pulse = ~load & load_dly;
 
always @ (posedge clk or load_pulse)
  if (load_pulse) q <= data;
  else q <= !q;



I'm sure there are other ways of using asynchronous preset and reset to generate a load pulse, but I'm not going to figure it out. I don't recommend using the above circuit it's likely to result in timing problems for the tools and would be very difficult to get the timing constraints right to ensure it works across temp/process.

Use at your own risk.
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
Unfortunately things don't work that way. Regular fabric flip-flops can only toggle on one edge of your choice. Not on both as you are trying to do now.
The only elements that do double datarate are things like ODDR (an OLOGIC resource), if on Xilinx.

Anyways, it's probably a good idea to clock your design on the posedge only.
 

maxxtorr723

Newbie level 5
Joined
Oct 19, 2013
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
64
What you are trying to describe is not a flip-flop that exists. There aren't any rising edge clocked, falling edge load registers in an FPGA.

You could do something hideous like this:

Code Verilog - [expand]
1
2
3
4
5
6
7
8
always @ (negedge clk)
  load_dly <= load;
 
assign load_pulse = ~load & load_dly;
 
always @ (posedge clk or load_pulse)
  if (load_pulse) q <= data;
  else q <= !q;



I'm sure there are other ways of using asynchronous preset and reset to generate a load pulse, but I'm not going to figure it out. I don't recommend using the above circuit it's likely to result in timing problems for the tools and would be very difficult to get the timing constraints right to ensure it works across temp/process.

Use at your own risk.

Thankyou sir for your timely reply!
I was also thinking to generate a small pulse using the load as you did but wont the logic assign load_pulse = ~load & load_dly; give a zero output while simulating in modelsim/Xilinx? Also the frequency of the PLL is not fixed so I dont think it is possible to give a predefined delay to load_dly <= load; as maybe at later stage we change the frequency and system becomes inoperable. Also I m okay with the loading of flipflop at positive edge, but in that case too the same problem will persist(i.e. the logic will keep on checking if Load=1 and as long as load is high it will not do the task of toggling)

- - - Updated - - -

Thank You mrflibble sir, But here I am not much concerned with which edge of the clock but rather on if we can start toggling the flipflop as soon as it is loaded on positive/negative edge of the clock(which then is used to generate down counter of N bit) but here due to level dependency on Load, a number of clock signals are wasted and I am not able to achieve frequency locking in PLL.
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
Why do you think you need to do the load on the negedge? Just make everything it synchronous to the posedge.

Something like:


Code Verilog - [expand]
1
2
3
4
5
6
7
8
//
// T flip-flop, synchronous load
// note that load is a boring sync signal
// 
 
always @(posedge clk) begin
    q <= (load) ? (t) : (q^t);
end

 
  • Like
Reactions: maxxtorr723

    V

    Points: 2
    Helpful Answer Positive Rating

    maxxtorr723

    Points: 2
    Helpful Answer Positive Rating

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
Thank You mrflibble sir, But here I am not much concerned with which edge of the clock but rather on if we can start toggling the flipflop as soon as it is loaded on positive/negative edge of the clock(which then is used to generate down counter of N bit) but here due to level dependency on Load, a number of clock signals are wasted and I am not able to achieve frequency locking in PLL.

I sort of follow what you say there, but don't see how that would become a problem. To avoid confusion, do you have a schematic of what you're trying to implement? The solution to this will depend on what the consumers of the T-flipflop output look like.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top