# Help in writing Verilog code for t flipflop with asynchronous Load.

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#### maxxtorr723

##### Newbie level 5
Hi, I am designing a jitter bounded DPLL in verilog for which I need a T flip-flop (for a down counter) which can toggle output on positive edge and load data asynchronously on negative edge. I wrote the code but it is not working as needed. Code is :-

Code Verilog - [expand]1
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data  , // Data Input
clk   , // Clock Input
q       // Q output
);
//-----------Input Ports---------------
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk or negedge load)
q <= data;
end else
begin
q <= !q;
end

endmodule //End Of Module tff_async_reset

The problem in this program is that even though the always@ block is activated at negative edge but since it checks if load=0 so say in case load is still at 0 and positive edge of clk arrives and the logic then checks to find that load=0 and again loads the data to q.
I am unable to figure out how to make this loading of data as edge triggered.

##### Super Moderator
Staff member
What you are trying to describe is not a flip-flop that exists. There aren't any rising edge clocked, falling edge load registers in an FPGA.

You could do something hideous like this:

Code Verilog - [expand]1
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always @ (negedge clk)

always @ (posedge clk or load_pulse)
else q <= !q;

I'm sure there are other ways of using asynchronous preset and reset to generate a load pulse, but I'm not going to figure it out. I don't recommend using the above circuit it's likely to result in timing problems for the tools and would be very difficult to get the timing constraints right to ensure it works across temp/process.

maxxtorr723

### maxxtorr723

Points: 2

#### mrflibble

Unfortunately things don't work that way. Regular fabric flip-flops can only toggle on one edge of your choice. Not on both as you are trying to do now.
The only elements that do double datarate are things like ODDR (an OLOGIC resource), if on Xilinx.

Anyways, it's probably a good idea to clock your design on the posedge only.

#### maxxtorr723

##### Newbie level 5
What you are trying to describe is not a flip-flop that exists. There aren't any rising edge clocked, falling edge load registers in an FPGA.

You could do something hideous like this:

Code Verilog - [expand]1
2
3
4
5
6
7
8
always @ (negedge clk)

always @ (posedge clk or load_pulse)
else q <= !q;

I'm sure there are other ways of using asynchronous preset and reset to generate a load pulse, but I'm not going to figure it out. I don't recommend using the above circuit it's likely to result in timing problems for the tools and would be very difficult to get the timing constraints right to ensure it works across temp/process.

- - - Updated - - -

Thank You mrflibble sir, But here I am not much concerned with which edge of the clock but rather on if we can start toggling the flipflop as soon as it is loaded on positive/negative edge of the clock(which then is used to generate down counter of N bit) but here due to level dependency on Load, a number of clock signals are wasted and I am not able to achieve frequency locking in PLL.

#### mrflibble

Why do you think you need to do the load on the negedge? Just make everything it synchronous to the posedge.

Something like:

Code Verilog - [expand]1
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//
// note that load is a boring sync signal
//

always @(posedge clk) begin
q <= (load) ? (t) : (q^t);
end

maxxtorr723

V
Points: 2

### maxxtorr723

Points: 2

#### mrflibble

Thank You mrflibble sir, But here I am not much concerned with which edge of the clock but rather on if we can start toggling the flipflop as soon as it is loaded on positive/negative edge of the clock(which then is used to generate down counter of N bit) but here due to level dependency on Load, a number of clock signals are wasted and I am not able to achieve frequency locking in PLL.

I sort of follow what you say there, but don't see how that would become a problem. To avoid confusion, do you have a schematic of what you're trying to implement? The solution to this will depend on what the consumers of the T-flipflop output look like.

maxxtorr723

Points: 2