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help in solving a problem with the AD6644 ADC

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tshankar501

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We have a small technical problem with the ADC evaluation board (AD6644) bought from Analog Devices. We would be thankful to you if you can help us in solving this problem. The description of this ADC and the actual problem we faced are given below.

ADC Description:
This ADC operates with a sampling rate of 65 Msps. A crystal oscillator is used to generate this frequency. This ADC has a 4 to 1 transformer in the front and a maximum peak to peak voltage of 0.5V is allowed to be given at the input pin.

Theoretical Calculation:
The calculation in the "ROLE OF ADC" paper by Brad Brennon and Chris Cloninger shows that this ADC has a noise floor of -98.7dBm. So we thought that a signal with a power greater than this (atleast -90dBm) would be detected by this ADC. Also an assumption was made in that paper that this ADC has an SFDR of about -90dBFS. So in order to achieve a C/I of about 18dB at the output, an input power of -67dBFS would be sufficient (considering the 4.8dBm of full scale input).

Problem:
We want to work with the lowest signal power at the front of ADC so that it could be placed as near to the antenna as possible in some applications. Presently, we are feeding a sinusoidal signal from the signal generator with 50 ohm output and we are observing the MSB of this 14 bit ADC. We find that this ADC works with a minimum power of only -50dBm. If we decrease the power below -50dBm, this ADC ceases to work i.e the MSB relation with the input is wrong.

Request:
We request you to provide the details of the minimum signal power requirement with which this ADC would operate satisfactorily and do we able to achieve.
 

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