It is a matter of strong on polarization, nmos saturation is stronger than pmos, that is why they are preffered for draining current from an output rather than sourcing current toward an output.
Its due to the fact that NMOS's drain can go to 0V without affecting the Vgs...and similarly PMOS's drain can go to Vdd without affecting the Vgs... so we can have 0 to Vdd swing...
Usually we connect source of pmos to the Vdd, and the source of the Nmos to the ground, Do this to easily control current. If the bias voltage is high, Pmos is almost off, then Vout ~ Vdd => logic 1. And when the bias voltage is low, Nmos is off, then Vout ~ Gnd => logic is 0.
Regard.