# help in correcting verilog code

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#### Manuv16589

##### Member level 1
hi there,
I am writing parallel adder using task. But i am getting error in code.The code is as follows

Code:
module demo(x,y, cin, s,cout);
parameter N=3;
input [N:0]x,y;
input cin;
output [N:0]s;
output cout;
reg cout;
reg [N:0]s;
reg [N+1:0]c;
integer i;
always@(x,y,cin)
begin
c[0]=cin;
for(i=0;i<=N;i=i+1)
cout<=c[N+1];
end
input a,b,cin;
output s,cout;
begin
s=a^b^cin;
cout=(a&b)|(b&cin)|(cin&a);
end

endmodule

The error is "ERROR:HDLCompilers:159 - "demo.v" line 35: Illegal argument passed to port 4 (output) of task 'faddr' ". what is this error? Please solve this problem. Thanks in advance.

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#### FvM

##### Super Moderator
Staff member
The error complains about y passed as output argument s of the task. y is an input and can't be assigned as output.

Do you know, that the arguments are assigned by order?

#### Manuv16589

##### Member level 1
The error complains about y passed as output argument s of the task. y is an input and can't be assigned as output.

Do you know, that the arguments are assigned by order?

I think i have passed the arguments correctly. I have passed y for b. Isnt it correct?

#### manojkhandelwal

##### Member level 2
first pass inputs in order and then outputs...not the other way around...you have passed y for s, and not b;
the argument order for your case should be x,y,c and then s,c[i+1]...

FvM

### FvM

Points: 2

#### Manuv16589

##### Member level 1
Yeah thanks...it worked

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