carrot
Full Member level 3
- Joined
- Feb 23, 2004
- Messages
- 182
- Helped
- 9
- Reputation
- 18
- Reaction score
- 4
- Trophy points
- 1,298
- Location
- Bangalore, India
- Activity points
- 1,532
failed to get a shared lock on library
Hi,
Anyone using NCVhdl?
The Cadence tool which i'am using is showing some errors when written testbench & compiled? but if it is written in verilog it does not show any error. Can anyone using NCVhdl can guide me.
Added after 1 minutes:
Hi,
Anyone using NCVhdl?
The Cadence tool which i'am using is showing some errors when written testbench & compiled for VHDL? but if it is written in verilog it does not show any error. Can anyone using NCVhdl can guide me.
Hi,
Anyone using NCVhdl?
The Cadence tool which i'am using is showing some errors when written testbench & compiled? but if it is written in verilog it does not show any error. Can anyone using NCVhdl can guide me.
Added after 1 minutes:
Hi,
Anyone using NCVhdl?
The Cadence tool which i'am using is showing some errors when written testbench & compiled for VHDL? but if it is written in verilog it does not show any error. Can anyone using NCVhdl can guide me.