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[SOLVED] help in behavioral modelling

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Shyam Joe

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I'm trying to code my algorithm in behavioral modelling in verilog code. the following is my code
Code Verilog - [expand]
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module fpadd(p,a,b,su1,su2);
input [255:0] p,a,b;
output reg [255:0] su1,su2;
wire c1,c2;
wire [255:0] v1,t1,t2,u;
wire [255:0] v2,w1,w2;
integer i;
parameter s=1;
initial
begin
for(i=0;i<256;i=i+1)
begin
if(b[i])
u=b;
else
u=a;
v1=u<<s;
v2=a+b;
w1=v1+(~p)+1;
w2=v2+(~p)+1;
c1=w1[3] | v1[3];
c2=w2[3] | v2[3];
if(c1)
t1=w1;
else
t1=v1;
if(c2)
t2=w2;
else
t2=v2;
if(b[i])
begin
su1=t1;
su2=t2;
end
else
begin
su1=t2;
su2=t1;
end
end
end
endmodule
[/syntax=verilog]
i get the following errors
Module <fpadd> compiled
ERROR:HDLCompilers:247 - "fpadd.v" line 14 Reference to vector wire 'u' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 14 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 16 Reference to vector wire 'u' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 16 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 17 Reference to vector wire 'v1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 17 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 18 Reference to vector wire 'v2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 18 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 19 Reference to vector wire 'w1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 19 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 20 Reference to vector wire 'w2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 20 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 21 Reference to scalar wire 'c1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 21 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 22 Reference to scalar wire 'c2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 22 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 24 Reference to vector wire 't1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 24 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 26 Reference to vector wire 't1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 26 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 28 Reference to vector wire 't2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 28 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 30 Reference to vector wire 't2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "fpadd.v" line 30 Illegal left hand side of blocking assignment
please help me to clear the errors. i have attached [ATTACH]97326._xfImport[/ATTACH]the algorithm also
 
[COLOR="silver"][SIZE=1]- - - Updated - - -[/SIZE][/COLOR]
 
When i change coding like dis 
[syntax=verilog]
module fpadd(p,a,b,su1,su2);
input [255:0] p,a,b;
output reg [255:0] su1,su2;
wire c1,c2;
wire [255:0] v1,t1,t2,u;
wire [255:0] v2,w1,w2;
integer i;
parameter s=1;
initial
begin
for(i=0;i<256;i=i+1)
begin
if(b[i])
u<=b;
else
u<=a;
v1<=u<<s;
v2<=a+b;
w1<=v1+(~p)+1;
w2<=v2+(~p)+1;
c1<=w1[3] | v1[3];
c2<=w2[3] | v2[3];
if(c1)
t1<=w1;
else
t1<=v1;
if(c2)
t2<=w2;
else
t2<=v2;
if(b[i])
begin
su1<=t1;
su2<=t2;
end
else
begin
su1<=t2;
su2<=t1;
end
end
end
endmodule
[/syntax=verilog]
i get these errors
Module <fpadd> compiled
ERROR:HDLCompilers:247 - "fpadd.v" line 14 Reference to vector wire 'u' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 14 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 16 Reference to vector wire 'u' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 16 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 17 Reference to vector wire 'v1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 17 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 18 Reference to vector wire 'v2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 18 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 19 Reference to vector wire 'w1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 19 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 20 Reference to vector wire 'w2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 20 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 21 Reference to scalar wire 'c1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 21 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 22 Reference to scalar wire 'c2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 22 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 24 Reference to vector wire 't1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 24 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 26 Reference to vector wire 't1' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 26 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 28 Reference to vector wire 't2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 28 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fpadd.v" line 30 Reference to vector wire 't2' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fpadd.v" line 30 Illegal left hand side of nonblocking assignment
 

You can't assign a value to a wire in sequential code.

I suggest learning Verilog instead of guessing the syntax.
 

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