Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Help] HSIM/VCS Co-Simulation: Undefined port in module instantiation

Status
Not open for further replies.

XJT12

Newbie level 2
Joined
May 16, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Greater Chicago
Activity points
1,304
Hi everyone,

When I was using HSIM/VCS to compile a Verilog-SPICE design, I got a compilation error.
The error message is as follows:

Error-[UPIMI-E] Undefined port in module instantiation
fpu_add_flat_nc.v, 6620
Port "QN" is not defined in module 'DFFX1' defined in "saed90nm.cdl", 2019
Module instance: DFFX1 fpu_add_exp_dp_i_add_exp_out1_q_reg_9_( .D (n2840),
.CLK (fpu_add_exp_dp_clk), .Q (fpu_add_exp_dp_add_exp_out1[9]), .QN
(n4846));


However, in the SPICE model of this cell, I do have the QN port defined:

.subckt DFFX1 CLK D Q QN VDD VSS
mmp03 net06 D VDD VDD p12 l = 0.1u w = 0.33u m = 1
mmp012 CLKP CLKN VDD VDD p12 l = 0.1u w = 0.21u m = 1
mmp7 net7 CLKN net2 VDD p12 l = 0.1u w = 0.45u m = 1
mmp1 net1 CLKP net06 VDD p12 l = 0.1u w = 0.33u m = 1
mmp12 net7 net8 net10 VDD p12 l = 0.1u w = 0.21u m = 1
mmp6 net1 net2 net4 VDD p12 l = 0.1u w = 0.33u m = 1
mmp8 net8 net7 VDD VDD p12 l = 0.1u w = 0.4u m = 1
mmp10 net10 CLKP VDD VDD p12 l = 0.1u w = 0.21u m = 1
mmp13 Q net8 VDD VDD p12 l = 0.1u w = 1.12u m = 1
mmp4 net4 CLKN VDD VDD p12 l = 0.1u w = 0.33u m = 1
mmp14 QN net7 VDD VDD p12 l = 0.1u w = 1.12u m = 1
mmp011 CLKN CLK VDD VDD p12 l = 0.1u w = 0.21u m = 1
mmp2 net2 net1 VDD VDD p12 l = 0.1u w = 0.33u m = 1
mmn14 QN net7 VSS VSS n12 l = 0.1u w = 0.56u m = 1
mmn8 net8 net7 VSS VSS n12 l = 0.1u w = 0.21u m = 1
mmn012 CLKP CLKN VSS VSS n12 l = 0.1u w = 0.21u m = 1
mmn1 net1 CLKN net06 VSS n12 l = 0.1u w = 0.21u m = 1
mmn13 Q net8 VSS VSS n12 l = 0.1u w = 0.5u m = 1
mmn2 net2 net1 VSS VSS n12 l = 0.1u w = 0.21u m = 1
mmn7 net7 CLKP net2 VSS n12 l = 0.1u w = 0.21u m = 1
mmn6 net1 net2 net6 VSS n12 l = 0.1u w = 0.21u m = 1
mmn03 net06 D VSS VSS n12 l = 0.1u w = 0.21u m = 1
mmn10 net12 CLKN VSS VSS n12 l = 0.1u w = 0.21u m = 1
mmn4 net6 CLKP VSS VSS n12 l = 0.1u w = 0.21u m = 1
mmn12 net7 net8 net12 VSS n12 l = 0.1u w = 0.21u m = 1
mmn011 CLKN CLK VSS VSS n12 l = 0.1u w = 0.21u m = 1


.ends DFFX1


This error seems quite strange and unusual to me. Is there anyone who met this kind of problems and happen to know how to fix it?

Thanks
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top