help,how to solve this PT setup violation

[tigerajs]

clock CLK_48M (rise edge) 0.00 0.00
clock source latency 0.00 0.00
clk_48m (in) 0.00 0.00 0.00 r
clk_48m (net) 34 0.00
u_clk_gen/clk_48m (clk_gen) 0.00 0.00 0.00 r
u_clk_gen/clk_48m (net)
u_clk_gen/u_clk_gate_rx_48m/clk (clk_gate_2)
0.00 0.00 0.00 r
u_clk_gen/u_clk_gate_rx_48m/clk (net)
u_clk_gen/u_clk_gate_rx_48m/U3/Y (AND2X2) 310.93 171.26 171.26 r
u_clk_gen/u_clk_gate_rx_48m/clk_out (net)
3941 53.59
u_clk_gen/u_clk_gate_rx_48m/clk_out (clk_gate_2)
0.00 0.00 171.26 r
u_clk_gen/clk_rx_48m (net)
u_clk_gen/clk_rx_48m (clk_gen) 0.00 0.00 171.26 r
clk_rx_48m (net)
u_modem/clk_rx_48m (modem) 0.00 0.00 171.26 r
u_modem/clk_rx_48m (net)
u_modem/u_rx_modem_fec_top/clk (rx_modem_fec_top)
0.00 0.00 171.26 r
u_modem/u_rx_modem_fec_top/clk (net)
u_modem/u_rx_modem_fec_top/fifo_trx_aa_reg[4]/CK (DFFRHQX1)
310.93 1.20 172.45 r
u_modem/u_rx_modem_fec_top/fifo_trx_aa_reg[4]/Q (DFFRHQX1)
0.79 -20.68 151.77 f
u_modem/u_rx_modem_fec_top/fifo_trx_aa[4] (net)
3 0.04
u_modem/u_rx_modem_fec_top/fifo_trx_aa[4] (rx_modem_fec_top)
0.00 0.00 151.77 f
u_modem/fifo_trx_aa[4] (net)
u_modem/fifo_trx_aa[4] (modem) 0.00 0.00 151.77 f
fifo_trx_aa[4] (net)
U21/Y (AND2X2) 0.13 0.40 152.17 f
fifo_trx_aa1[4] (net) 2 0.03
u_fifo/fec_trx_fifo_waddr[4] (fifo) 0.00 0.00 152.17 f
u_fifo/fec_trx_fifo_waddr[4] (net)
u_fifo/u_fifo_ctrl/fec_trx_fifo_waddr[4] (fifo_ctrl)
0.00 0.00 152.17 f
u_fifo/u_fifo_ctrl/fec_trx_fifo_waddr[4] (net)
u_fifo/u_fifo_ctrl/U49/Y (NOR3X1) 0.43 0.32 152.50 r
u_fifo/u_fifo_ctrl/n54 (net)
1 0.01
u_fifo/u_fifo_ctrl/U59/Y (NAND4X1) 0.24 0.14 152.64 f
u_fifo/u_fifo_ctrl/n51 (net)
1 0.01
u_fifo/u_fifo_ctrl/U56/Y (NOR3X1) 0.62 0.42 153.06 r
u_fifo/u_fifo_ctrl/net50 (net)
2 0.02
u_fifo/u_fifo_ctrl/fec_trx_fifo_a_full_d_reg/D (DFFRHQX1)
0.62 0.00 153.06 r
data arrival time 153.06

clock CLK_48M (rise edge) 20.83 20.83
clock source latency 0.00 20.83
clk_48m (in) 0.00 0.00 20.83 r
clk_48m (net) 34 0.00
u_fifo/clk_tx_48m (fifo) 0.00 0.00 20.83 r
u_fifo/clk_tx_48m (net)
u_fifo/u_fifo_ctrl/clk_tx_48m (fifo_ctrl) 0.00 0.00 20.83 r
u_fifo/u_fifo_ctrl/clk_tx_48m (net)
u_fifo/u_fifo_ctrl/fec_trx_fifo_a_full_d_reg/CK (DFFRHQX1)
0.00 0.00 20.83 r
clock uncertainty -0.20 20.63
library setup time -0.18 20.45
data required time 20.45
-----------------------------------------------------------------------------
data required time 20.45
data arrival time -153.06
-----------------------------------------------------------------------------
slack (VIOLATED) -132.


why there is 171.26 delay, thanks. clk_tx_48m is the gate clock of CLK_48M,thanks

 

[tigerajs]

？？？？？ what's mean

 

[matter]

The straight answer is "there is a delay of 171.26 bcos the design looks horrendous". With the limited details gives, it is hard to point out the problem.

But my guess is that you are trying to run PT on a pre-CTS design. It looks like the clock trees are not built. But you are trying to time it in PT as if it were a post CTS design. i.e. You are propagating the clocks without building them. If you want to time your design in a pre-CTS mode, please set your clocks as ideal. i.e. do remove_propagated_clock [get_clocks *] or do set_ideal .. [get_clocks *]

 

[tigerajs]

thanks，i have solve it