[help]how to construct a circuit to test the phase margin

[xuanzhu]

I want to test the gain phase margin of an opamp, and I want to know how to construct such a circuit. My opinion is that if this circuit can commplete this test, it must be a negative feedback loop at not DC condition but AC condition. Can anyone help me?

 

[tecsiun]

can you use the tool--Hspice?
in the AC set: AC=1 ,then .ac
vp(OUT)

 

[electronrancher]

you can't use spice to test a circuit, only to simulate one.. haha

xuanzhu do you have a network analyzer at your company? gain phase of an op-amp is probably in the manual! anyway, you can set it up as negative feedback (DC) to give a gain of -10 or so. now you need to inject AC into the inverting terminal, and measure the return that is coming back to the place you are injecting.

we have a small transformer module where the network analyzer connects to the primary, and you break the op-amp loop with the secondary. now the dc condition just sees a wire, but AC is easily swept.


if you don't have a network analyzer, I would say to set up a gain=1 network, but this time drive the noninverting terminal with a 0-2V step voltage, as sharp as you can get it. now look at the transient response, is it ringing? that's low PM. is it really slow and rounded? low GBW. i think gray & meyer have plots of transient step response vs phase margin to give you an idea of what to compare to.

 

[xuanzhu]

is it really slow and rounded? low GBW. i think gray & meyer have plots of transient step response vs phase margin to give you an idea of what to compare to.

Sorry, I can not understand what this mean, and I don't know the network analyzer
I think your opinion is that if I want to simulate the phase margin without network analyzer, I must construct an voltage follower which must be a negative feedback loop at AC condition to run, and change the noninverting terminal voltage to guarantee the correct operating point. Is that right?

 

[electronrancher]

yes - go ahead and set it up for gain=1 voltage follower, and apply voltage steps to the + input. your DC condition should be satisfied by the fact that it's a follower. 1v-2v steps may be better just to keep it away from the bottom rail - maybe your amp saturates at low Vout, so a 1.5v common mode like this may be better.

you should get an idea of the phase margin from looking at oscilloscope response to the voltage steps , just viewing the settling time characteristics. it's crude, but without a network analyzer it's the best way i think.

to calcualte gain, set it up for a few different DC gains, maybe 10, 100, and 1000. now apply test voltages of 10mv, 100mv, 1v to the noninverting input. you can calculate the gain based on how well the output followed. if you need a better example i can try to set one up in spice in the next few days.


make sure not to load down your amp - using 1Ohm and 100Ohm for gain=100 isn't going to work well unless you have a really powerful amp. on the other side, remember that bjt have input bias current so for 100nA Ib you get 1mV offset for 100k resistor. CMOS does not have this problem so 10k-100k is a good range..

you'll need to hand-pick or match your resistors as precision is the key here. use the true measured value of the resistors when calculating.


read through this link, which is a good explanation too
**broken link removed**

other than that - i think you have it!

 

[xuanzhu]

Re: [help]how to construct a circuit to test the phase margi

I constructed the circuit to be a voltage follower and simulated it and found that the offset is very small: when '+' terminal voltage is 1.0v, the output voltage is 0.9985v, at this condition, the current source and the differential pair are all saturated, which is the expected outcome. But after I simuated the ac char of this circuit in the ac open loop condition, I found that the phase-frequence curve of the output signal has a very large change that the phase is from -180 degree to 180 degree. I can not understand why it has a so large change, and I can not affirm whether this phase margin value is fit. The following images are respectively the simulating circuit, the output DB gain-frequency curve, the output phase-frequency curve, and the phase margin value curve, pls help me!

**broken link removed**

 

[Hughes]

Re: [help]how to construct a circuit to test the phase margi

I found that the phase-frequence curve of the output signal has a very large change that the phase is from -180 degree to 180 degree. I can not understand why it has a so large change

Phase changes form -180 degree to 180 because hspice limits the phase in the range of -180~180. To get a continuous phase plot, "UNWRAP" option should be used.
.option unwrap
.probe ac phase=vp(out)

The parameter 'phase' will be plotted continuously. Other phase outputs not included in probe will still have a incontinuous curve however.

 

[xuanzhu]

thank Hughes and electronrancher
This netlist is derived from a low voltage comparator
I think this opamp is not good because the phase shifting of the output signal has exceed 180 degree.
Do you think so?