[HELP] GLOBAL CLOCK in Xilinx ISE?

[billjoe]

bufgctrl_x0y1

Q1. In ISE , How to make sure the clock is routed to GCLOCK?
even set clock to BUFG , still feel the DFF ( COUNTER) delay to large, HOW to Check GCLOCK DELAY in ISE?

Q2. What different between BUFG and BUFGMUX?

Q3. Any document mention about how to set GCLOCK PLACE/CONSTRAIN in your design ?

 

[EDALIST]

1. you can check the post p@r timing report.
also here is how to make sur you use BUFG correctly


snippest from UCF File :
================
Locate DCM/BUFG - Tools can probably figure them out automatically
# but just LOC them down to be safe
INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;

INST dcm_0/dcm_0/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y0;
INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;

INST dcm_1/dcm_1/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y31;
INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;


2. BUFGMUX As Is Name States Is A 2: 1 Clock Signals Mux to 1 global clock.

3. just check the help menu.

 

[gliss]

You can use Floorplanner to manually configure GCLOCK.