Help for UVM pack in verification

[gopimithun]

Hi,

There are 2 types,
In which there are some fields in it.

Eg:
TYPE 1: [7:0]src,[7:0]dest,xtype,[4:0]ytype ,[16:0]a , [16:0]b , [16:0]c , [16:0]d
TYPE 2: [7:0]src,[7:0]dest,xtype,[4:0]ytype ,[16:0]w, [16:0]x , [16:0]y , [16:0]z

I want to pack all the fields in TYPE 1 and TYPE 2 and send it byte by byte,
But when I do run with TYPE 1 I want to transmit only the TYPE 1 fields.
I am confused how to pack these 2 type with different fields in it , though some fields in TYPE 1 and TYPE 2 are same.
I used single uvm_sequence_item, were all the fields are written.
I used pack_bytes() for sending byte by byte,
But I am unable to take only the TYPE 1 fields.
I don’t want the fields of TYPE 2 when I am running with TYPE 1.
Is there any way to do this using UVM.

thanks,
Gopi

 

[dave_59]

You need to be more specific about what a "type" is. Is it a mode bit, or something else. Why are they not two different extensions of the uvm_sequence item class

A good place to ask UVM questions is https://verificationacademy.com/forum/verification-methodology-discussion-forum/uvm-forum

 

[gopimithun]

Hi Dave,
Thanks for your reply..
Actullay TYPE 1 and TYPE 2 are two different sequence_item only.
But i have a doubt weather we can have more than one sequence_item., if so how to call that sequence_item alone in different classes. I mean monitor,Scoreboard,etc...

thanks,
Gopi