help for pipeline adc problem

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rainman.cn

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can anyone show me something about
digital correction in pipeline adc or
give me a intuitional unstanding about that ?
its really puzzle me.
thx,
 

"Wrong" digital code output in pre-stage brings "wrong" reference added to multiplying DAC so as to "wrong" digital code still, but addition of two "wrong" code gives wanted correct code.
 

Thanks for replies,
what I donnt know is why the additional code can give our wanted code.
can you detail it ?
thanks very much,
 

the additional code (additional comparator) avoids the input of the next stage to be saturated (larger that |Vref| ) in presence of comparator offset. draw the characteristics for 1b and 1.5b stages!
 

    rainman.cn

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1 The digital output is overlap each stage, then they can be added.
2 The decision line deviation each stage must less than ±1/2(1/Gi - 1/Ni)Fs that can guarantee the correction result right.
Where Gi is i-th stage gain. Ni is number of i-th stage ADC code.
Detail you can reference CMOS data converters for communication p235-239
 

    rainman.cn

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