Help for "Error : does not hold value outside clk edge&

[GeekWizard]

Hello,

I am trying to compile a VHDL code written by another person. I am getting this error for a number of signals.

Error (10818): Can't infer register for "S_PLLValid" at DeviceControl.vhd(67) because it does not hold its value outside the clock edge

The Quartus Help file apparently does not provide any details on this error.

Fix the problem identified by the message text. A future version of the Quartus II software will provide more extensive Help for this error message.

Can anyone help what the reason is and how can the error be corrected?

 

[haneet]

Re: Help for "Error : does not hold value outside clk e

i am not sure but i guess there is some hold violation in the coding.

if you could post the code it might help to some extent

bye

 

[GeekWizard]

Re: Help for "Error : does not hold value outside clk e

Here is the part of code that deals with the signal 'S_PLLValid'. I tried to mark the signal as bold but apparently it doesnt highlight under the code tag, so I've indicated using arrows.

signal S_PLLValid:STD_LOGIC;                        <----------- 

process(Reset,Clock,RS232InInt,PLLValid)
  begin
	  if(Reset='1') then
		  PLL1Output<=(Others=>'0');	PLL2Output<=(Others=>'0');
		  PLL3Output<=(Others=>'0');
		  I_PLLOutput<=0;				I_Nibble<=1;
		  I_WordNumber<=1;				S_PLLValid<='0';                               <-----------
		  I_PLLOutputNibble1<=0;		I_PLLOutputNibble2<=0;
		  I_PLLOutputNibble3<=0;
	  elsif (RS232InInt'Event and RS232InInt='0' and S_PLLControl='1') then
		  if (I_Nibble=1) then
			  I_PLLOutputNibble1<=CONV_INTEGER(InputFromRS232(7 downto 4));
			  I_PLLOutputNibble2<=CONV_INTEGER(InputFromRS232(3 downto 0));
			  I_Nibble<=2;
		  elsif (I_Nibble=2) then 
			  I_PLLOutputNibble3<=CONV_INTEGER(InputFromRS232(3 Downto 0));
			  I_Nibble<=3;
		  end if;
	  elsif (I_Nibble=3) then
		  I_PLLOutput<=I_PLLOutputNibble1*100+I_PLLOutputNibble2*10+I_PLLOutputNibble3;
		  I_Nibble<=4;
	  elsif (I_Nibble=4) then			  
		  if(I_PLLOutput<512) then
			  if(S_PLL1Control='1') then
				  PLL1Output<=CONV_STD_LOGIC_VECTOR(I_PLLOutput,9);
			  elsif(S_PLL2Control='1') then
				  PLL2Output<=CONV_STD_LOGIC_VECTOR(I_PLLOutput,9);
			  elsif(S_PLL3Control='1') then
				  PLL3Output<=CONV_STD_LOGIC_VECTOR(I_PLLOutput,9);
			  end if;
		  end if;
		  I_Nibble<=1;
 	  elsif(PLLValid'Event and PLLValid='1') then
		 I_PLLOutput<=CONV_INTEGER(PLL);
		 S_PLLValid<='1';    <-----------
	  elsif(S_PLLValid='1') then       <----------- 
		S_PLLValid<='0';     <-----------
		if(I_WordNumber=1) then
			PLL1Output<=CONV_STD_LOGIC_VECTOR(I_PLLOutput,9);
			I_WordNumber<=2;
		elsif(I_WordNumber=2) then
			PLL2Output<=CONV_STD_LOGIC_VECTOR(I_PLLOutput,9);
			I_WordNumber<=3;
		elsif(I_WordNumber=3) then
			PLL3Output<=CONV_STD_LOGIC_VECTOR(I_PLLOutput,9);
			I_WordNumber<=1;
		end if;		  
	 end if;
 end process;

Thanks !

 

[j_andr]

Re: Help for "Error : does not hold value outside clk e

/.../

your code is awfull ... ;

 elsif(PLLValid'Event and PLLValid='1') then 
       I_PLLOutput<=CONV_INTEGER(PLL); 
       S_PLLValid<='1';            <--- 
       elsif(S_PLLValid='1') then  <--- 
        S_PLLValid<='0';           <----

the piece above tells the synthesis tool:
I need a FlipFlop with its clock input connected to PLLValid,
the FF should get '1' when clock goes high and then it has to
go immediately to '0';
in other words - you require the hardware to change its output
after the clock slope, what is in principe not allowed;

if you really intend to get such behaviour use S_PLLValid signal
as an async. reset signal;

something like this [I work with verilog, so this is an idea only]

process ( PLLValid, S_PLLValid )
if (S_PLLValid = '1') then
S_PLLValid <= '0';
elsif (PLLValid'Event and PLLValid='1') then
S_PLLValid <= '1';

good luck;