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help design bandgap voltage reference circuit.

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triquent

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I am trying to design the bandgap voltage reference circuit. (The Opamp+pnpBJT type)The spec. Vdd=2.5V Vout=1.25V Itotal<10uA. I can design the resistance R1 and R2 by dVout/dT=0 and get Vout =1.25V. But the Vout change too much with the Temperature, Vdd. Also PSRR is too large. PSRR=-40db at DC. But psrr almost equal 0 at 1GHz.
My question is
1) how to design the pmos size?
2) how to design the op_amp size?
3) how to improve the Vout insensitivity to T, Vdd. And PSRR?
4) can we discuss the design procedure? how to get every transistor's size? i am a new beginner totally confused.
 

electronrancher

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well, this is not quite a bandgap. this circuit makes a ptat current of (kt/q)ln(n)/R.

ptat is proportional to absolute temp - it is linearly rising with temp.

in order to get a magic voltage, you need to dump this current into a diode plus resistor. diode voltage drops with temp, so scale the resistor to cancel the two slopes to give a flat voltage at room. it may not be exactly 1.25v, every process has a different magic voltage - even two cells in the same process may have different voltages for the flat area at room.

pmos size should be long and large to match. scale the pmos to have vdsat=150mV and you should be OK. longer pmos (or more op-amp gain) will reduce sensitivity to Vdd/PSRR (same thing). try for op amp gain of 55-65dB. any more and you'll have a hard time to stabilize - i suggest just using a simple op amp out of any CMOS book.

can you upload your plot of vout vs temp - that should help
 

    Anokhi

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triquent

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Thankd!
how to scale the pmos size to have vdsat=150mv. I thought the vdsat is fixed since the model is given. what do you mean the pmos size need to be long and large? long means length? large means width?
I will upload my vdd vs temp curve next time. the spec need vdd change within 5mV over 0~100C. but my more 10mv.

electronrancher said:
well, this is not quite a bandgap. this circuit makes a ptat current of (kt/q)ln(n)/R. don't know how to reduce the temp sensitivity.

ptat is proportional to absolute temp - it is linearly rising with temp.

in order to get a magic voltage, you need to dump this current into a diode plus resistor. diode voltage drops with temp, so scale the resistor to cancel the two slopes to give a flat voltage at room. it may not be exactly 1.25v, every process has a different magic voltage - even two cells in the same process may have different voltages for the flat area at room.

pmos size should be long and large to match. scale the pmos to have vdsat=150mV and you should be OK. longer pmos (or more op-amp gain) will reduce sensitivity to Vdd/PSRR (same thing). try for op amp gain of 55-65dB. any more and you'll have a hard time to stabilize - i suggest just using a simple op amp out of any CMOS book.

can you upload your plot of vout vs temp - that should help
 

crazyamd

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read Grey or Lee's books before you go any further....
 

rongli

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I think first choose the erramp's size,it's about 3-5times of the most small size.then concider the current source and reference voltage type.
 

electronrancher

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vdsat=sqrt(Id/(2*k'*W/L)) depending on the current level, targeting vdsat=150mv will give you W/L for a device. 100mV or 120mV is OK too if you want to get a bit more agressive.

Let's say you have a mosfet with W/L=10 and Id=10uA that give vdsat=150mV. Now for 20uA and the same vdsat, all you need to do is make W/L=20. That will speed you up somewhat.
 

triquent

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thanks. now I have got the good vref vs temp and vref vs Vdd. Both change within 4mV. Now my question is how to design good PSRR. The Op-Amp gain is large? how to check the Op_Amp 's gain?

Added after 7 minutes:

Forget to say the spec for PSRR is vrefdB<-50db at DC and vrefdB<-40dB from DC to 1GHz when applying ac signal at vdd. I checked paper, never saw people have such small PSRR at high frequency. usually in the paper at high frequency psrr close to 0dB. I don't know if the professor is wrong.
Also the transient simulation need vref deviation <2mV when applying a pulse 2.5~2.8V at Vdd. I got 200mV deviation.
Any suggestions?

Added after 39 minutes:

This is my PSRR simulation results.
 

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