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[help]DDR sdram controller design in a chip

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albred

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debugging sdram designs

I am puzzled about the STA requirement of the design,and where can I find some material about it? thanks
 

luancao

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ddr timing diagrams

To make it simple, let's descibe in the following way.

First, you will have a clear specification in your DDR controller interface. The timing diagram specified the frequency, duty cycle, setup, hold time etc, in most cases, with max and min in a range.

Then, you convert this timing specification to the controller equivallent time. That is, you specify the timing requirement in your design that satisfies the timing diagram your specification. After you get it done, you will have to check the timing in SPEC one by one to see if each of them are satisfied and there is no confliction in them.

Finally, you write the above timing reqirement in the script of the STA tools and debug it to make it work in your STA enviroment.


You could find some example. But I think it may spend more time than just get it from the SPEC timing diagram.
 

bc70

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sdram controller+tutorial

Look on synopsys solvnet - they used to have a pretty good app note describing how to time DDR with STA.
 

odeafeiner

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sdram controller design tutorial

hi,

But how about setting the requirement of pre_amble/post_amble of the timing
requirement of DDR? I had trouble with them when i try setting them with primetime constraint.

Thanks,

luancao said:
To make it simple, let's descibe in the following way.

First, you will have a clear specification in your DDR controller interface. The timing diagram specified the frequency, duty cycle, setup, hold time etc, in most cases, with max and min in a range.

Then, you convert this timing specification to the controller equivallent time. That is, you specify the timing requirement in your design that satisfies the timing diagram your specification. After you get it done, you will have to check the timing in SPEC one by one to see if each of them are satisfied and there is no confliction in them.

Finally, you write the above timing reqirement in the script of the STA tools and debug it to make it work in your STA enviroment.


You could find some example. But I think it may spend more time than just get it from the SPEC timing diagram.
 

albred

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dll design for ddr sdram

luancao said:
To make it simple, let's descibe in the following way.

First, you will have a clear specification in your DDR controller interface. The timing diagram specified the frequency, duty cycle, setup, hold time etc, in most cases, with max and min in a range.

Then, you convert this timing specification to the controller equivallent time. That is, you specify the timing requirement in your design that satisfies the timing diagram your specification. After you get it done, you will have to check the timing in SPEC one by one to see if each of them are satisfied and there is no confliction in them.

Finally, you write the above timing reqirement in the script of the STA tools and debug it to make it work in your STA enviroment.


You could find some example. But I think it may spend more time than just get it from the SPEC timing diagram.

the controller has a digital dll inside,and the dll can be tune by some programble parammeter to get the delay you want.
but how should I choose the appropriate delay?before physical place&route and board route,I can't get the right delay I want.
 

luancao

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sdram controller tutorial

the controller has a digital dll inside,and the dll can be tune by some programble parammeter to get the delay you want.
but how should I choose the appropriate delay?before physical place&route and board route,I can't get the right delay I want.

The DLL should be coped as a Macro. Therefore add the timing constrain from the output pin the DLL depending on how your DDR IF is designed. For example, if your DLL generates 10 clocks from the input of the DDR CK, then one of the clock is selected programmable, it is quite safe for you to add the constrain to ensure the difference of the delay at your data to IO and the delay at your clock to IO less than 1/10 the DDR clock. Then other timing reqirements will meet by program the phase of the clock by a training or other process.
 

amanath

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dll training sdram

I need the basics of dll .. can any body upload any tutorial or text book
 

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