Help: Create IO pad using Encounter

[Asmah Truky]

Hello...

I'm a first time user of nano encounter. How to create a blank IO pad using Encounter? I've tried to look around for simple instruction but couldn't find any.
Given only the technology LEF file, do I need to create my own IO pad LEF?

Thank you

 

[joe2moon]

Yes. Technology LEF library is not enough.
-------------------------------------------------

You have to prepare I/O pad LEF library with other tools, such as Virtuoso.

 

[Asmah Truky]

Oh ok...

Thank you joe2moon

 

[p_shinde]

where would i get to read on this , as how to prepare this file??????


Prasad

 

[arimilli_r]

Hi Prasad,
Check your tech LEF file , it should contain the IO cell information,if it doesnt have that information, contact your library team, because we have to design IO cell and layout it using virtuso(icfb) .
If that was not ready with your library team :

--Ask what are the input and output pins and approximate loactions of those pins.
--Create a BLACK BOX using nano encounter.
BlackBox : Is a dummy module with the pin information.

You can use this in your design and go ahead until your IO team gets the info.

--Arimilli Rajesh

 

[p_shinde]

Rajesh can i have your email address if possible, as there are some more doubts in this things.

If u want u can mail me to shinde.prasad@gmail.com , so that i can have ur email address.


Thanks,
Prasad

 

[arimilli_r]

Hi u can reach me at Arimilli.Rajesh@gmail.com

 

[shankarmit]

yes you need a lef file ask your vendor to give lef file for pad cells..

you just edit you netlist and add component io pads for all in and out pins.. and then will importing lef file it automatically regonises as pad cells and it fill place it around the core.. and add filler to fill the gap..

regards

shankar
tallika

 

[p_shinde]

PDIDGZ Pibiasip(
.PAD(ibias),
.C(ibiasI));

if i am rgt this is oe of pad cells in the lef file whjich i found, can anyone tell how do we write it?????


here are some more of data copied from lef file

PDIDGZ Prefclkip(
.PAD(refclk),
.C(refclkI));

PDIDGZ Pintip(
.PAD(int),
.C(intI));
do we manually have to write it for all pins??????


thanks, pls reply soon, if any documents on how to write this fille, would be grt

Prasad

 

[shankarmit]

hi check that you took this line from lef file.. because u have to write similarly in netlist also.

it simple just declare output pin names as signal name1...
then you just have that PDIZG(Something) as component connecting name1 with output pin names..

change the topmodule names as name1 etc....



Regards
Shankar
tallika