the_phoenix
Newbie level 6
shift left +std_logic_vector
PLEASE HELP ME WITH THIS CODE...I GET some weird error in this code...
U can even try pasting the code in any vhdl s/w n check..i work with xilinx ise!!!
**
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file c:\xilinx\bin\123/123.vhd, automatic determination of correct order of compilation of files in project file shift_left_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file c:\xilinx\bin\123/123.vhd in Library work.
ERROR:HDLParsers:164 - c:\xilinx\bin\123/123.vhd Line 19. parse error, unexpected AFFECT, expecting COMMA or COLON
**
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_left is
Generic (size:integer:=4);
Port ( a : in std_logic_vector(size-1 downto 0);
x,y,z : out std_logic_vector(size-1 downto 0));
end shift_left;
architecture Behavioral of shift_left is
Function slar (arg1:=STD_LOGIC_VECTOR; arg2:=NATURAL)
Return STD_LOGIC_VECTOR is
Variable input: STD_LOGIC_VECTOR(size-1 downto 0):=arg1;
constant size:integer:=arg1'LENGTH;
variable copy:STD_LOGIC_VECTOR(size-1 downto 0)
:=(others=>arg1(arg1'RIGHT));
variable result: STD_LOGIC_VECTOR (size-1 downto 0);
begin
IF (arg2=>size-1) then result:=copy;
else result:=input(size-1-arg2 downto 1) & copy(arg2 downto 0);
END IF;
RETURN RESULT;
END slar
begin
x<=slar(a,0);
y<=slar(a,1);
z<=slar(a,2);
end Behavioral;
Added after 1 minutes:
line 19 is the line where the definition of the function begins...i mean ..with the arguments arg1 and arg2!!
PLEASE HELP ME WITH THIS CODE...I GET some weird error in this code...
U can even try pasting the code in any vhdl s/w n check..i work with xilinx ise!!!
**
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file c:\xilinx\bin\123/123.vhd, automatic determination of correct order of compilation of files in project file shift_left_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file c:\xilinx\bin\123/123.vhd in Library work.
ERROR:HDLParsers:164 - c:\xilinx\bin\123/123.vhd Line 19. parse error, unexpected AFFECT, expecting COMMA or COLON
**
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_left is
Generic (size:integer:=4);
Port ( a : in std_logic_vector(size-1 downto 0);
x,y,z : out std_logic_vector(size-1 downto 0));
end shift_left;
architecture Behavioral of shift_left is
Function slar (arg1:=STD_LOGIC_VECTOR; arg2:=NATURAL)
Return STD_LOGIC_VECTOR is
Variable input: STD_LOGIC_VECTOR(size-1 downto 0):=arg1;
constant size:integer:=arg1'LENGTH;
variable copy:STD_LOGIC_VECTOR(size-1 downto 0)
:=(others=>arg1(arg1'RIGHT));
variable result: STD_LOGIC_VECTOR (size-1 downto 0);
begin
IF (arg2=>size-1) then result:=copy;
else result:=input(size-1-arg2 downto 1) & copy(arg2 downto 0);
END IF;
RETURN RESULT;
END slar
begin
x<=slar(a,0);
y<=slar(a,1);
z<=slar(a,2);
end Behavioral;
Added after 1 minutes:
line 19 is the line where the definition of the function begins...i mean ..with the arguments arg1 and arg2!!