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HELP:CODE COMPILATION ERROR WITH A SHIFT LEFT FUNCTION!!!

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the_phoenix

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shift left +std_logic_vector

PLEASE HELP ME WITH THIS CODE...I GET some weird error in this code...
U can even try pasting the code in any vhdl s/w n check..i work with xilinx ise!!!
**
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file c:\xilinx\bin\123/123.vhd, automatic determination of correct order of compilation of files in project file shift_left_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file c:\xilinx\bin\123/123.vhd in Library work.
ERROR:HDLParsers:164 - c:\xilinx\bin\123/123.vhd Line 19. parse error, unexpected AFFECT, expecting COMMA or COLON
**

CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shift_left is
Generic (size:integer:=4);
Port ( a : in std_logic_vector(size-1 downto 0);
x,y,z : out std_logic_vector(size-1 downto 0));
end shift_left;

architecture Behavioral of shift_left is

Function slar (arg1:=STD_LOGIC_VECTOR; arg2:=NATURAL)
Return STD_LOGIC_VECTOR is
Variable input: STD_LOGIC_VECTOR(size-1 downto 0):=arg1;
constant size:integer:=arg1'LENGTH;
variable copy:STD_LOGIC_VECTOR(size-1 downto 0)
:=(others=>arg1(arg1'RIGHT));
variable result: STD_LOGIC_VECTOR (size-1 downto 0);

begin
IF (arg2=>size-1) then result:=copy;
else result:=input(size-1-arg2 downto 1) & copy(arg2 downto 0);
END IF;
RETURN RESULT;
END slar

begin
x<=slar(a,0);
y<=slar(a,1);
z<=slar(a,2);
end Behavioral;

Added after 1 minutes:

line 19 is the line where the definition of the function begins...i mean ..with the arguments arg1 and arg2!!
 

vlsi_whiz

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Re: HELP:CODE COMPILATION ERROR WITH A SHIFT LEFT FUNCTION!

The problem with your code is that in the function declaration you used the assignment operator :)=) instead of the port/ input-output operator:)). The second mistake is in the function body... IF (arg2 => size-1) THEN ..the comparision operator is wrong here....this (=>) again is the port mapping operator. I think you wanted to compare the two and when replaced with >= (greater than equal to) operator the code compiles correctly.

Here's the corrected code.. Hope this helps!

Code:
LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.STD_LOGIC_ARITH.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY SHIFT_LEFT IS
GENERIC (size:integer:=4);
PORT ( a : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
       x,
       y,
       z : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END;

ARCHITECTURE Behavioral OF shift_left IS

FUNCTION slar (arg1:STD_LOGIC_VECTOR; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
   VARIABLE input : STD_LOGIC_VECTOR(size-1 DOWNTO 0):=arg1;
   CONSTANT size  : INTEGER:=arg1'LENGTH;
   VARIABLE copy  : STD_LOGIC_VECTOR(size-1 DOWNTO 0):=(OTHERS=>arg1(arg1'RIGHT));
   VARIABLE result: STD_LOGIC_VECTOR (size-1 DOWNTO 0);

BEGIN
  IF (arg2 >= size-1) THEN 
    result:=copy;
  ELSE 
    result:=input(size-1-arg2 DOWNTO 1) & copy(arg2 DOWNTO 0);
  END IF;
  RETURN RESULT;
END slar;

BEGIN
x<=slar(a,0);
y<=slar(a,1);
z<=slar(a,2);
END;
 

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