help: CMOS FOLDER circuit

[aindejeje]

i try to design a cmos folder with 4x folding.
according to theory it should:
switch to HIGH at (vref1 and vref3)
switch to LOW at (vref2 and vref4)

but i got different characteristic.
i tried to vary sizing,regulate current at NMOS-source,and replace the PMOS with conventional resistors.but all produced almost the same output.
can anyone tell me whats wrong with it? :?:

here is my SPICE code:

vvdd      vdd	0   2.5
vvref1    vref1   0   0.5
vvref2    vref2   0   1
vvref3    vref3   0   1.5
vvref4    vref4   0   2

VIN VIN GND PWL (0 0 1u 2.5)

.tran/op 10n 1u
.print	V(v+,v-) V(vin)

.END

 

[kickbeer]

hi jeje,

Which resolution should your ADC have?

 

[aindejeje]

8bits~
probably reduce the resolution if it is too hard for me