Help Clock Gating - PT STA said timing violated

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Help Clock Gating

Hi,

I am wondering why PT STA said timing violated but with different clock start point

13020.00 and 13022.00
what do this mean?




==============
Report : timing
-path full
-delay min
-max_paths 1
****************************************


Startpoint: digital/uart_txframer/push2_reg
(rising edge-triggered flip-flop clocked by clock_uart')
Endpoint: digital/uart_txframer/clk_gate_data_adc_g_reg/latch
(negative level-sensitive latch clocked by clock_uart')
Path Group: clock_uart
Path Type: min

Point Incr Path
------------------------------------------------------------------------------
clock clock_uart' (rise edge) 13020.00 13020.00
clock network delay (propagated) 0.72 * 13020.72
digital/uart_txframer/push2_reg/CP (DFCN1Q) 0.00 13020.72 r
digital/uart_txframer/push2_reg/Q (DFCN1Q) 0.29 * 13021.01 r
digital/uart_txframer/clk_gate_data_adc_g_reg/EN (SNPS_CLOCK_GATE_HIGH_uart_txframer)
0.00 * 13021.01 r
digital/uart_txframer/clk_gate_data_adc_g_reg/latch/D (LN1Q)
0.00 * 13021.01 r
data arrival time 13021.01

clock clock_uart' (rise edge) 13022.00 13022.00
clock network delay (propagated) 0.72 * 13022.72
digital/uart_txframer/clk_gate_data_adc_g_reg/latch/EN (LN1Q) 13022.72 r
library hold time -0.08 * 13022.64
data required time 13022.64
------------------------------------------------------------------------------
data required time 13022.64
data arrival time -13021.01
------------------------------------------------------------------------------
slack (VIOLATED) -1.63