process(clk)
variable tal1, tal2: std_logic_vector(7 downto 0 );
variable result: std_logic_vector(15 downto 0 );
variable temp_operand: std_logic_vector(2 downto 0 );
begin
if rising_edge(clk) then
case state is
when s0 =>
if operand /="000" then
temp_operand := operand;
dispx(7 downto 0 ) <= switch(7 downto 0 );
dispx(15 downto 8 ) <="11101110";
tal1 := switch(7 downto 0 );
state <= s1;
else
dispx(7 downto 0 ) <= switch(7 downto 0 );
dispx(15 downto 8 ) <= "11101110";
end if;
when s1 =>
if equal='1' then
tal2 := switch(7 downto 0 );
case temp_operand is
when "100" =>
result := ("00000000"&tal1) + tal2;
when "010" =>
result := ("00000000"&tal1) - tal2;
when others =>
result := tal1*tal2;
end case;
dispx <= result;
state <= s2;
else
dispx(7 downto 0 ) <= switch(7 downto 0 );
dispx(15 downto 8 ) <= "11101110";
end if;
when s2 =>
if switch /= tal2 then
state <= s0;
else
state <= s2;
dispx <= result;
end if;
when others =>
state <= s0;
end case;
end if;
end process;