DE2 is a Cyclone II FPGA eval board, not a FPGA.
In has on-board parallel flash, so it could theoretically store passwords, but I guess that's beyond the scope of this exercise problem. It's probably fine to have the passwords stored in FPGA registers or block RAM, preloaded with default content, editable but lost when you shut down the power.
Similarly, I presume the exercise doesn't involve encryption…
To organize sequential process flow (e.g. of an "ATM") in hardware logic, you need to build a finite state machine (or multiple hierarchical FSM). Best start to sketch a state diagrams of the intended function. Start with simple parts like the multiple digit password entry.
- - - Updated - - -
Although sorting algorithms may be used, they aren't necessary for a basic implementation. No problem to compare an entered password against all stored values without previous sorting. Start to define some parameters minimal and maximal password length, used alphabet, necessary control keys (at least backspace and enter, I guess).
- - - Updated - - -
That looks O.K. for the top level state machine. There must be lower level state machines for the keyboard entry.