help: about using the Mentor Graphic's FPGA Advantage 5.4

[eruca]

graphic fpga

Hi, I am using the FPGA Advantage 5.4.There is a problem when I followed the getting started guide to learn whether the soft could work well.I imported the sample codes just as the help paper doing,cleared the error and started the Modelsim. when i tried to set probes,the modelsim exited with the following message:

Data preparation step completed, check transcript...
---------------------------------------------------------------------------------
Reading D:/FPGAdv53/Modeltech/tcl/vsim/pref.tcl
Reading D:/FPGAdv53/Hds/resources/downstream/modelsim/hdsInit.tc_
Connected to HDS
# Attempting stack trace sig 11
# Signal caught: signo [11]
# vsim_stacktrace.vstf written
# Current time Wed Apr 16 22:11:46 2003
# ModelSim Stack Trace
# Program = vsim
# Id = "5.6a"
# Version = "2002.04"
# Date = "Apr 29 2002"
# Platform = win32
# 0 0x004ef741: '<unknown (@0x4ef741)> + 0x59211'
# 1 0x004ef787: '<unknown (@0x4ef787)> + 0x59257'

# Corrupt Call Stack

** Fatal: (SIGSEGV) Bad pointer access. Closing vsim.
vsim is exiting with code 211

Could anyone help me with this problem?

Thanks!!

 

[arena_yang]

Hi friend,

I had gotten some training on FPGA Advantage.but I have no the s/w at hand now, so I can't repeat the error you run in.

But I think whether you could run/simulate your design in a Modelsim enviorment separately not invoke it in the HDL Designer.