Help?About @ltera and sy*plicity

[homeadd]

I meet a strange problem about synplicity for @ltera.
I use AC1K30 in my design and synplicity 7.23 for synthesis.Sometimes the synthesis may take few minutes,but the other time can not complete ,even hours!
When I change the chip from @ltera to Xilinx,example XC2S30,the synthesis speed will be so quick.
Can somebody help me?

 

[Mentor2003]

Try an other family of Altera

 

[TurboPC]

I meet a strange problem about synplicity for @ltera.
I use AC1K30 in my design and synplicity 7.23 for synthesis.Sometimes the synthesis may take few minutes,but the other time can not complete ,even hours!
When I change the chip from @ltera to Xilinx,example XC2S30,the synthesis speed will be so quick.
Can somebody help me?

It has been my experience that the usage of arrays as block RAMs can slow down Synplify by a factor of 10! It is weird, but and I think this has been solved in later releases. Here's my fix:

attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "no_rw_check";

By specifying the "no_rw_check" attributes, Synplify becomes intelligent and does not lose time anymore when synthetizing RAMs.

Hope this helps!

TurboPC