help about comparator design.

[triquent]

I am trying to design a 64bit signed comparator in verilog. Anyone has some good example?
I am wondering if I only can compare it one bit by one bit (from the MSB to LSB) and get results? Is there a simple way to do it?

 

[nand_gates]

Hi,
You can refer to CD4585 4-bit comparator data sheet for more info.
You will have to write verilog module for CD4585. Instantiate this one
16 times to get 64 bit comparator. Other option is if ur using Synopsys
DC then go for DesignWare comparators. If you want to target for FPGA
you can use coregen to generate 64 bit comparator for you.