help: 2to1 decoder in vhdl

[abba]

i need a 2to1 decoder with dual clock in (rising edge!).
(or another one with this true-table:
RESET A_CLK D_CLK OUT
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 x x 0
)

i've a little problem with this because im a newby in vhdl. - thanx

this is my source:
###########
entity decoder_2to1 is
Port ( RESET : in STD_LOGIC;
A_CLK : in STD_LOGIC;
D_CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC
);
end decoder_2to1;

architecture Behavioral of decoder_2to1 is

begin


process(A_CLK, D_CLK, RESET)
begin

if ( RESET = '1') then
D_OUT <= '0';
elsif ( A_CLK'event and A_CLK ='1') then
D_OUT <= '0';
elsif ( D_CLK'event and D_CLK ='1') then
D_OUT <= '1';
end if;

end process;

end Behavioral;

this is the error message (xilinx- project navigator):
#################################
Analyzing Entity <decoder_2to1> (Architecture <behavioral>).
ERROR:Xst:827 - D:/xilinx/busmonitor/d10_andreas_home/decoder_2to1.vhd line 30: Signal d_out cannot be synthesized, bad synchronous description.
-->

 

[mitaka]

can you explain what exactly you want

1.)as i see from the true table - there is no matter A_clk in what stage is - always OUT is =not D_CLK

2.) from the code i fill that you want to catch the rising edge of A_CLK or D_CLK

 

[yygetit]

8O

1. It's impossible to use dual clock in a process using VHDL.
2. What means 2to1 decoder???
there is no clock event concept in truth table for A_ and D_clk
if u want 2to4 decoder with clock
how about use this st.

ss <= A_Clk & D_Clk;
process(clk, reset)
begin
if reset = '1' then
D_out <= '1'
elsif (clk='1' and clk'event)
if ss = "00" then
D_out <= '1';
elsif ss="01" then
D_out <= '0';
....
else
D_out <= '0';
end if;
end if;
end process;

 

[visualart]

Why do you select verilog? The verilog is easy to learn and to use.